pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 275

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
2.3.1 The Signal Monitoring Mode
A double DMA buffer scheme is used. The base start addresses for both DMA buffers
in every queue is programmable as is the size of the DMA buffers. The SIZE
parameter allows DMA buffers to be up to 1 Megabyte. Both DMA buffer work in a
ping-pong fashion which forces the use of both of them.
Any of the GPIO pins or the internal signals listed in
signal monitoring. Only the GPIO pins can be selected for pattern generation.
The layout of the MMIO register is found in
Selection of the GPIO or internal signals to monitor can be found in
The signal monitoring mode is an extension of the event monitoring that uses the 12
timestamp units. The signals, i.e. GPIO pins and the internal signals) can be
monitored in two different ways:
GPIO MMIO Description for Signal Monitoring FIFO queues
The FIFO queues are controlled by the GPIO_EV[3:0] MMIO registers. The status of
the sampling and the interrupt control MMIO registers are INT_STATUS[3:0],
INT_ENABLE[3:0] and INT_CLEAR[3:0]. INT_SET[3:0] is only meant for software
debug (used to trigger the hardware interrupt but using software). In the following text
a ‘x’ may be used to refer to one of the 4 MMIO registers, e.g. GPIO_EVx or one of
the two flags, like BUFx_RDY for BUF2_RDY or BUF2_RDY.
Upon reset, signal monitoring is disabled (GPIO_EV[3:0].FIFO_MODE and
GPIO_EV[3:0].EVENT_MODE = 00), and the DMA buffer 1 is the active DMA buffer.
Software initiates signal monitoring by providing, per FIFO, two equal size empty
DMA buffers and putting their base address and size in the relevant BASE1_PTRx,
BASE2_PTRx and SIZEx MMIO registers. Once two valid DMA buffers are assigned,
monitoring can be enabled by programming the relevant GPIO_EVx.FIFO_MODE
and GPIO_EVx.EVENT_MODE. For the enabled FIFOs, the GPIO hardware will
proceed to fill the DMA buffer 1 with timestamps or samples. Once DMA buffer 1 fills
up, INT_STATUSx.BUF1_RDY is asserted, and monitoring continues a seamless
transfer in DMA buffer 2. If INT_ENABLEx.BUF1_RDY_EN is enabled, an interrupt
request is generated to the chip level interrupt controller, the VIC block in TM3260.
The interrupt should be configured in the VIC block in level triggered mode.
When INT_STATUSx.BUF1_RDY is high, software is required to assign a new empty
buffer to BASE1_PTRx and then clear the INT_STATUSx].BUF1_RDY flag (by writing
a ‘1’ to INT_CLEARx.BUF1_RDY_CLR), before buffer 2 fills up which prevents an
overrun.
•
•
Event Timestamping: Using an event timestamps whenever a signal changes
state. In this case the FIFO queues are filled with 32-bit timestamp values as
defined in
Signal Sampling: Sampling the signal value at a programmable frequency. In this
mode up to 4 signals per FIFO can be grouped for sampling. The FIFO are filled
up with the signal values at each sampling clock edge.
Section
Rev. 3 — 17 March 2006
2.2.2.
Chapter 8: General Purpose Input Output Pins
Section
4.4,
Section 2.2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Section 4.5
PNX15xx Series
can be selected for
and
Section
Section
4.15.
4.11.
8-8