cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 10
cy8c5588pvi-115es0
Manufacturer Part Number
cy8c5588pvi-115es0
Description
Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CY8C5588PVI-115ES0.pdf
(102 pages)
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The Cortex-M3 CPU subsystem includes these features:
■
■
■
■
■
■
■
■
Document Number: 001-44094 Rev. *J
ARM Cortex-M3 CPU
Programmable nested vectored interrupt controller (NVIC),
tightly integrated with the CPU core
Full featured debug and trace modules, tightly integrated with
the CPU core
Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB
of SRAM
Cache controller
Peripheral HUB (PHUB)
DMA controller
External memory interface (EMIF)
SRAM
SRAM
32 KB
32 KB
Interrupt Inputs
JTAG/SWD
Bus
Matrix
Bus
Matrix
Debug Block
AHB Spokes
(Serial and
Controller
Vectored
Interrupt
Nested
(NVIC)
JTAG)
GPIO &
EMIF
AHB
I- Bus
Figure 4-1. ARM Cortex-M3 Block Diagram
AHB Bridge & Bus Matrix
PRELIMINARY
C-Bus
D-Bus
AHB
Digital
Prog.
Cortex M3 CPU Core
Peripherals
PHUB
AHB
S-Bus
Cortex M3 Wrapper
Analog
Prog.
4.0.1 Cortex-M3 Features
The Cortex-M3 CPU features include:
■
■
■
■
4 GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and
simultaneous accesses of instructions, data, and peripherals.
The Thumb
performance at Thumb-level code density. This includes 16-bit
and 32-bit instructions. Advanced instructions include:
❐
❐
❐
❐
❐
❐
❐
Bit-band support. Atomic bit-level write and read operations.
Unaligned data storage and access. Contiguous storage of
data of different byte lengths.
The Cortex-M3 does not support ARM instructions.
PSoC
Bit-field control
Hardware multiply and divide
Saturation
If-Then
Wait for events and interrupts
Exclusive access and barrier
Special register access
DMA
Bus
Matrix
Functions
®
Special
®
Watchpoint and
Instrumentation
-2 instruction set, which offers ARM-level
and Breakpoint
5: CY8C55 Family Datasheet
Trace Module
Trace (DWT)
Flash Patch
(FPB)
(ITM)
Data
Cache
Trace Module
Interface Unit
Embedded
Trace Port
(TPIU)
(ETM)
256 KB
Flash
ECC
Trace Pins:
5 for TRACEPORT or
1 for SWV mode
Page 10 of 102
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