cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 42

• Manufacturer Part Number: cy8c5588pvi-115es0
• Description: Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
• Manufacturer: Cypress Semiconductor Corporation.

8. Analog Subsystem
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
■
■
■
The PSoC Creator software program provides a user friendly
interface to configure the analog connections between the GPIO
and various analog resources and also connections from one
analog resource to another. PSoC Creator also provides
component libraries that allow you to configure the various
analog blocks to perform application specific functions (PGA,
transimpedance amplifier, voltage DAC, current DAC, and so
on). The tool also generates API interface libraries that allow you
to write firmware that allows the communication between the
analog peripheral and CPU/Memory.
8.1 Analog Routing
The CY8C38 family of devices has a flexible analog routing
architecture that provides the capability to connect GPIOs and
Document Number: 001-44094 Rev. *J
Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses
High resolution Delta-Sigma ADC
Two successive approximation (SAR) ADCs
GPIO
Port
A
N
A
L
O
G
R
O
U
T
N
G
I
ADC
Figure 8-1. Analog Subsystem Block Diagram
SAR
DAC
DAC
PRELIMINARY
Array
DSI
CMP
SC/CT Block
SC/CT Block
CapSense Subsystem
CMP
Comparators
Distribution
Interface
Analog
Clock
CMP
SC/CT Block
SC/CT Block
■
■
■
■
■
■
different analog blocks, and also route signals between different
analog blocks. One of the strong points of this flexible routing
architecture is that it allows dynamic routing of input and output
connections to the different analog blocks.
8.1.1 Features
■
■
■
Four 8-bit DACs that provide either voltage or current output
Four comparators with optional connection to configurable LUT
outputs
Four configurable switched capacitor/continuos time (SC/CT)
blocks for functions that include opamp, unity gain buffer,
programmable gain amplifier, transimpedance amplifier, and
mixer
Four opamps for internal use and connection to GPIO that can
be used as high current output buffers
CapSense subsystem to enable capacitive touch sensing
Precision reference for generating an accurate analog voltage
for internal analog blocks
Flexible, configurable analog routing architecture
16 analog globals (AG) and two analog mux buses
(AMUXBUS) to connect GPIOs and the analog blocks
Each GPIO is connected to one analog global and one analog
mux bus
Registers
PSoC
Config &
Reference
Status
Precision
CMP
Decimator
®
5: CY8C55 Family Datasheet
PHUB
SAR
ADC
DAC
DAC
CPU
A
N
A
L
O
G
R
O
U
T
N
G
I
GPIO
Port
Page 42 of 102
[+] Feedback
[+] Feedback
[+] Feedback
[+] Feedback