cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 3
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cy8c5588pvi-115es0
Manufacturer Part Number
cy8c5588pvi-115es0
Description
Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CY8C5588PVI-115ES0.pdf
(102 pages)
- Current page: 3 of 102
- Download datasheet (3Mb)
1. Architectural Overview
Introducing the CY8C55 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C55 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Document Number: 001-44094 Rev. *J
0. 5 to 5.5 V
( Optional )
32.768 KHz
( Optional )
( Optional )
4- 33 MHz
System Wide
Resources
Clocking System
Power Management
Xtal
Osc
IMO
1.8 V LDO
POR and
System
Power
Timer
Sleep
Wake
SMP
WDT
LVD
RTC
ILO
and
Digital Interconnect
PRELIMINARY
Figure 1-1. Simplified Block Diagram
EEPROM
8- Bit
I 2C Slave
Timer
UART
Temperature
EMIF
LCD Direct
UDB
UDB
UDB
UDB
( TIA, PGA, Mixer etc)
CapSense
Memory System
Sensor
Drive
4 x SC / CT Blocks
Universal Digital Block Array (24 x UDB)
Quadrature Decoder
8- Bit SPI
UDB
UDB
UDB
UDB
FLASH
SRAM
4 x DAC
Digital
12- Bit SPI
Logic
12- Bit PWM
Block
Filter
Digital System
UDB
UDB
UDB
UDB
16- Bit
PWM
System Bus
16- Bit PRS
8- Bit
Timer
Analog Interconnect
UDB
UDB
UDB
UDB
Logic
PSoC
Cortex M3 CPU
Analog System
ADCs
Controller
8051 or
Cache
UDB
UDB
UDB
UDB
CPU System
®
UDB
UDB
UDB
UDB
SAR
ADC
Del Sig
2 x
ADC
1 x
5: CY8C55 Family Datasheet
Controller
Interrupt
PHUB
DMA
Counter
Timer
PWM
4 x
CAN
2.0
Opamp
CMP
4 x
4 x
Program &
Boundary
Program
Debug
Debug &
+
+
-
-
Trace
FS USB
Scan
Master /
Slave
I2C
2.0
USB
PHY
Opamp
3 per
Page 3 of 102
22
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