cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 38

• Manufacturer Part Number: cy8c5588pvi-115es0
• Description: Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
• Manufacturer: Cypress Semiconductor Corporation.

Figure 7-29. Digital System Interconnect
Interrupt and DMA routing is very flexible in the CY8C55
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design.
(Interrupt/DMA Multiplexer).
Figure 7-30. Interrupt and DMA Processing in the IDMUX
7.0.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
Document Number: 001-44094 Rev. *J
Fixed Function DRQs
Counters
Clocks
Global
Timer
Fixed Function IRQs
Figure 7-30
Global
Clocks
CAN
UDB Array
EMIF
I2C
shows the structure of the IDMUX
Interrupt and DMA Processing in IDMUX
Digital System Routing I/F
Digital System Routing I/F
Delta-
Sigma
ADC
IRQs
DRQs
UDB ARRAY
Controller
Interrupt
ADC
SAR
Detect
Detect
Edge
Edge
Controller
Blocks
DMA
SC
0
1
2
0
1
2
3
PRELIMINARY
DACS
IO Port
DMA termout (IRQs)
Pins
Comparators
Controller
Controller
Interrupt
DMA
IO Port
Pins
option to be double synchronized. The synchronization clock is
the system clock (see
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-31. I/O Pin Synchronization Routing
Figure 7-32. I/O Pin Output Connectivity
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
Figure 7-33. I/O Pin Output Enable Connectivity
4 IO Control Signal Connections from
DO
UDB Array Digital System Interface
DI
PIN 0
PSoC
OE
PIN 0
DO
8 IO Data Output Connections from the
UDB Array Digital System Interface
PIN1
OE
®
PIN1
DO
5: CY8C55 Family Datasheet
PIN2
OE
PIN2
DO
Figure
PIN3
OE
PIN3
DO
Port i
6-1). Normally all inputs from pins
Port i
PIN4
OE
PIN4
DO
PIN5
OE
PIN5
DO
PIN6
OE
PIN6
DO
Page 38 of 102
PIN7
PIN7
OE
DO
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