cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 24

• Manufacturer Part Number: cy8c5588pvi-115es0
• Description: Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
• Manufacturer: Cypress Semiconductor Corporation.

6.1 Reset
CY8C55 has multiple internal and external reset sources
available. The reset sources are:
■
■
■
■
Figure 6-7. Resets
The term system reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register holds the source of the most recent reset
or power voltage monitoring interrupt. The program may
examine this register to detect and report exception conditions.
This register is cleared after a power on reset.
6.0.1 Reset Sources
6.0.1.1 Power Voltage Level Monitors
■
Document Number: 001-44094 Rev. *J
Reset
Pin
Power source monitoring - The analog and digital power
voltages, V
several different modes during power up, active mode, and
sleep mode (buzzing). If any of the voltages goes outside
predetermined ranges then a reset is generated. The monitors
are programmable to generate an interrupt to the processor
under certain conditions before reaching the reset thresholds.
External - The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull-up to Vddio1. V
have voltage applied before the part comes out of reset.
Watchdog timer - A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset.
Software - The device can be reset under program control.
IPOR - Initial Power on Reset
At initial power on, IPOR monitors the power voltages V
and V
DDA
Vddd Vdda
Watchdog
Monitors
Software
External
Register
Voltage
, both directly at the pins and at the outputs of the
DDA
Power
Reset
Timer
Reset
Level
, V
DDD
, V
CCA
DDD
, and V
Controller
, V
Reset
DDA
CCD
, and Vddio1 must all
are monitored in
PRELIMINARY
System
Processor
Reset
Interrupt
DDD
■
■
Table 6-1. Analog/Digital Low Voltage Interrupt, Analog High
Voltage Interrupt
6.0.1.2 Other Reset Sources
■
Interrupt Supply
PRES - Precise Low Voltage Reset
ALVI, DLVI, AHVI - Analog/Digital Low Voltage Interrupt, Analog
High Voltage Interrupt
XRES - External Reset
AHVI
corresponding internal regulators. The trip level is not precise.
It is set to approximately 1 volt, which is below the lowest
specified operating voltage but high enough for the internal
circuits to be reset and to hold their reset state. The monitor
generates a reset pulse that is at least 100 ns wide. It may be
much wider if one or more of the voltages ramps up slowly.
To save power the IPOR circuit is disabled when the internal
digital supply is stable. Voltage supervision is then handed off
to the precise low voltage reset (PRES) circuit. When the
voltage is high enough for PRES to release, the IMO starts.
This circuit monitors the outputs of the analog and digital
internal regulators after power up. The regulator outputs are
compared to a precise reference voltage. The response to a
PRES trip is identical to an IPOR reset.
In normal operating mode, the program cannot disable the
digital PRES circuit. The analog regulator can be disabled,
which also disables the analog portion of the PRES. The
PRES circuit is disabled automatically during sleep and
hibernate modes, with one exception: During sleep mode the
regulators are periodically activated (buzzed) to provide
supervisory services and to reduce wakeup time. At these
times the PRES circuit is also buzzed to allow periodic voltage
monitoring.
Interrupt circuits are available to detect when V
go outside a voltage range. For AHVI, V
fixed trip level. For ALVI and DLVI, V
compared to trip levels that are programmable, as listed in
Table
a device reset instead of an interrupt.
DLVI
ALVI
The monitors are disabled until after IPOR. During sleep
mode these circuits are periodically activated (buzzed). If an
interrupt occurs during buzzing then the system first enters its
wakeup sequence. The interrupt is then recognized and may
be serviced.
CY8C55 has either a single GPIO pin that is configured as an
external reset or a dedicated XRES pin. Either the dedicated
XRES pin or the GPIO pin, if configured, holds the part in reset
PSoC
6-1. ALVI and DLVI can also be configured to generate
®
V
V
V
DDD
DDA
DDA
5: CY8C55 Family Datasheet
1.71 V-5.5 V 1.70 V-5.45 V in
1.71 V-5.5 V 1.70 V-5.45 V in
1.71 V-5.5 V 5.75 V
Normal
Voltage
Range
250 mV
increments
250 mV
increments
Available Trip
Settings
DDA
DDA
is compared to a
and V
DDA
Page 24 of 102
Accuracy
and V
DDD
±2%
±2%
±2%
DDD
are
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