cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 18

• Manufacturer Part Number: cy8c5588pvi-115es0
• Description: Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
• Manufacturer: Cypress Semiconductor Corporation.

Table 6-1. Oscillator Summary
6.0.1 Internal Oscillators
6.0.1.2 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±1% accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±1% at 3 MHz, up to ±7% at 74 MHz. The
IMO, in conjunction with the PLL, allows generation of CPU and
system clocks up to the device's maximum frequency (see
Phase-Locked
The IMO provides clock outputs at 3-, 6-, 12-, 24-, 48-, and
74-MHz.
Document Number: 001-44094 Rev. *J
MHzECO
kHzECO
Source
Doubler
IMO
DSI
PLL
ILO
Loop)
7
12-48 MHz
24 MHz
12 MHz
3-74 MHz
32 kHz
3 MHz
4 MHz
0 MHz
1 kHz
Doubler
Fmin
IMO
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
±1% over voltage and
temperature
Crystal dependent
Input dependent
Input dependent
Input dependent
–50%, +100%
Crystal dependent
Tolerance at Fmin
4-33 MHz
ECO
24-80 MHz
PLL
PRELIMINARY
Figure 6-1. Clocking Subsystem
External IO
0-66 MHz
or DSI
100 kHz
74 MHz
33 MHz
66 MHz
80 MHz
48 MHz
32 kHz
Fmax
Clock Mux
Divider 16 bit
Divider 16 bit
Divider 16 bit
Divider 16 bit
Digital Clock
Digital Clock
Digital Clock
Digital Clock
System
32 kHz ECO
±7%
Crystal dependent
Input dependent
Input dependent
Input dependent
–55%, +100%
Crystal dependent
6.0.1.3 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works for input frequency ranges of 6 to
24 MHz (providing 12 to 48 MHz at the output). It can be
configured to use a clock from the IMO, MHzECO, or the DSI
(external pin). The doubler is typically used to clock the USB.
6.0.1.4 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
Tolerance at Fmax
PSoC
1,33,100 kHz
®
ILO
5: CY8C55 Family Datasheet
7
10 µs max
5 ms typ, max is crystal dependent
Input dependent
250 µs max
1 µs max
15 ms max in lowest power mode
500 ms typ, max is crystal dependent
Bus Clock Divider
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
Analog Clock
Divider 16 bit
16 bit
Startup Time
s
k
e
w
s
k
e
w
s
k
e
w
s
k
e
w
Clock
CPU
Clock
Bus
Page 18 of 102
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