mc68hc908lj24 Freescale Semiconductor, Inc, mc68hc908lj24 Datasheet - Page 143

• Manufacturer Part Number: mc68hc908lj24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

9.3.1 Bus Timing
9.3.2 Clock Start-up from POR or LVI Reset
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
STOP MODE CLOCK
ENABLE SIGNALS
FROM CONFIG2
OSC2
OSC1
PHASE-LOCKED LOOP (PLL)
OSCILLATOR (OSC) MODULE
CGMRCLK
In user mode, the internal bus frequency is either the oscillator output
(CGMXCLK) divided by four, CGMXCLK divided by two, or the PLL
output (CGMPCLK) divided by four.
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 ICLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this
entire period. The IBUS clocks start upon completion of the timeout.
Figure 9-3. CGM Clock Signals
System Integration Module (SIM)
CGMOUT
SIMDIV2
CGMXCLK
ICLK
SYSTEM INTEGRATION MODULE
SIM COUNTER
÷ 2
TO RTC, ADC
SIM Bus Clock Control and Generation
System Integration Module (SIM)
GENERATORS
GENERATORS
BUS CLOCK
USER MODE
MONITOR MODE
SIMOSCEN
Data Sheet
PTC1
IT12
TO REST
OF MCU
IT23
TO REST
OF MCU
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