mc68hc908lj24 Freescale Semiconductor, Inc, mc68hc908lj24 Datasheet - Page 345

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mc68hc908lj24

Manufacturer Part Number
mc68hc908lj24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Addr.
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ADC Data Register High
ADC Data Register High
ADC Data Register Low
ADC Data Register Low
Register Name
Register Name
Figure 16-8. ADRH and ADRL in Left Justified Sign Data Mode
(ADRH)
(ADRH)
(ADRL)
(ADRL)
Figure 16-7. ADRH and ADRL in Left Justified Mode
In left justified mode the ADRH holds the eight most significant bits
(MSBs), and the ADRL holds the two least significant bits (LSBs), of the
10-bit result. The ADRH and ADRL are updated each time a single
channel ADC conversion completes. Reading ADRH latches the
contents of ADRL. Until ADRL is read all subsequent ADC results will be
lost. (See
In left justified sign mode the ADRH holds the eight MSBs with the MSB
complemented, and the ADRL holds the two least significant bits (LSBs),
of the 10-bit result. The ADRH and ADRL are updated each time a single
channel ADC conversion completes. Reading ADRH latches the
contents of ADRL. Until ADRL is read all subsequent ADC results will be
lost. (See
Mode.)
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Bit 7
Bit 7
AD9
AD1
AD9
AD1
Analog-to-Digital Converter (ADC)
R
R
R
R
0
0
0
0
Figure 16-7 . ADRH and ADRL in Left Justified
Figure 16-8 . ADRH and ADRL in Left Justified Sign Data
AD8
AD0
AD8
AD0
R
R
R
R
6
0
0
6
0
0
AD7
AD7
R
R
R
R
5
0
0
0
5
0
0
0
AD6
AD6
R
R
R
R
4
0
0
0
4
0
0
0
AD5
AD5
R
R
R
R
3
0
0
0
3
0
0
0
Analog-to-Digital Converter (ADC)
AD4
AD4
R
R
R
R
2
0
0
0
2
0
0
0
AD3
AD3
R
R
R
R
1
0
0
0
1
0
0
0
Mode.)
I/O Registers
Data Sheet
Bit 0
Bit 0
AD2
AD2
R
R
R
R
0
0
0
0
0
0
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