mc68hc908lj24 Freescale Semiconductor, Inc, mc68hc908lj24 Datasheet - Page 150

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mc68hc908lj24

Manufacturer Part Number
mc68hc908lj24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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System Integration Module (SIM)
9.6 Exception Control
9.6.1 Interrupts
Data Sheet
150
INTERRUPT
INTERRUPT
MODULE
MODULE
I-BIT
I-BIT
R/W
R/W
IAB
IDB
IAB
IDB
DUMMY
DUMMY
Normal, sequential program execution can be changed in three different
ways:
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
Figure 9-9
SP – 4
SP
Figure 9-9. Interrupt Recovery Timing
PC – 1[7:0] PC – 1[15:8]
Figure 9-8. Interrupt Entry Timing
Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
Reset
Break interrupts
CCR
SP – 1
SP – 3
System Integration Module (SIM)
shows interrupt recovery timing.
A
SP – 2
SP – 2
X
X
Figure 9-8
SP – 3
SP – 1
PC – 1[15:8] PC – 1[7:0]
A
SP – 4
SP
shows interrupt entry timing, and
CCR
VECT H
PC
MC68HC908LJ24/LK24 — Rev. 2.1
V DATA H
OPCODE
VECT L
PC + 1
OPERAND
V DATA L
Freescale Semiconductor
START ADDR
OPCODE

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