dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 11

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

RX_DV
RX_ER
RXD_0
RXD_1
RXD_2
RXD_3
CRS/CRS_DV
COL
Signal Name
RX_DV
RX_ER
RXD_0
RXD_1
RXD_2
RXD_3
CRS/CRS_DV
COL
Pin Name
S, O, PU
S, O, PD
S, O, PU
S, O, PU
O, PD
Type
Pin #
39
41
46
45
44
43
40
42
MII RECEIVE DATA VALID: Asserted high to indicate that valid data is
present on the corresponding RXD[3:0].
RMII RECEIVE DATA VALID: This signal provides the RMII Receive
Data Valid indication independent of Carrier Sense.
This pin provides an integrated 50 ohm signal termination, making
external termination resistors unnecessary.
MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to
indicate that an invalid symbol has been detected within a received packet
in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever a
media error is detected, and RX_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in RMII mode, since the PHY
is required to corrupt data on a receive error.
This pin provides an integrated 50 ohm signal termination, making
external termination resistors unnecessary.
MII RECEIVE DATA: Nibble wide receive data signals driven
synchronously to the RX_CLK (25 MHz for 100 Mb/s mode, 2.5 MHz for
10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is
asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven
synchronously to the 50 MHz reference clock.
These pins provide integrated 50 ohm signal terminations, making
external termination resistors unnecessary.
MII CARRIER SENSE: Asserted high to indicate the receive medium is
non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines
the RMII Carrier and Receive Data Valid indications. For a detailed
description of this signal, see the RMII Specification.
This pin provides an integrated 50 ohm signal termination, making
external termination resistors unnecessary.
MII COLLISION DETECT: Asserted high to indicate detection of a
collision condition (simultaneous transmit and receive activity) in 10 Mb/
s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is
also asserted for a duration of approximately 1µs at the end of
transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is
always logic 0. There is no heartbeat function during 10 Mb/s full duplex
operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is
required. The MAC will recover CRS from the CRS_DV signal and use
that along with its TX_EN signal to determine collision.
This pin provides an integrated 50 ohm signal termination, making
external termination resistors unnecessary.
11
Description
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