dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 68

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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15:14
8:2
Bit
13
12
11
10
14.2.9 PHY Control Register 2 (PHYCR2)
This register provides additional general control.
9
1
0
CLK_OUT RXCLK
SYNC_ENET EN
PHYTER_COMP
CLK_OUT_DIS
SOFT_RESET
RESERVED
RESERVED
RESERVED
BC_WRITE
Bit Name
TABLE 35. PHY Control Register 2 (PHYCR2), address 0x1C
0 0000 00, RO
Strap, RW
0, RW/SC
Default
00, RO
0, RW
0, RW
0, RW
0, RW
0, RW
RESERVED: Writes ignored, read as 0.
Synchronous Ethernet Enable:
When this bit is 1 and the device is in 100 Mb/s mode, and the MAC
interface is either MII or RMII Master, enables fully synchronous
communication relative to the recovered receive clock. The transmitter
is synchronized to the receiver.
When this bit is 0 or the device settings do not match the above
conditions, the transmitter is synchronous to the local reference clock.
Enable RX_CLK on CLK_OUT:
When this bit is 1 and the device is in 100 Mb/s mode, the 25 MHz
recovered receive clock (RX_CLK) is driven on CLK_OUT in addition
to RX_CLK. When this bit is 0 or the device is in 10 Mb/s mode,
CLK_OUT reflects the Reference clock.
Broadcast Write Enable:
1 = Enables the Serial Management Interface to accept register writes
to PHY Address of 0x1F independent of the local PHY Address value.
0 = Normal operation
Phyter Compatibility Mode:
1 = Enables Phyter (DP83848) Compatible pinout. Reorders the RX MII
pins and Autonegotiation straps to match the DP83848. Also enables
the CLK_OUT output.
0 = Normal operation
Soft Reset:
Resets the entire device minus the registers - all configuration is
preserved.
1 = Reset, self-clearing.
RESERVED: Writes ignored, read as 0.
Disable CLK_OUT Output:
Disables the CLK_OUT output pin.
RESERVED: Must be zero.
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Description