dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 60

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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14.2.3 100 Mb/s PCS Configuration and Status Register (PCSR)
This register contains control and status information for the 100BASE Physical Coding Sublayer.
Bit
15
11
10
9
8
7
6
5
4
3
2
AUTO_CROSSOV
FORCE_100_OK
SD FORCE PMA
NRZI_BYPASS
SD_OPTION
DESC_TIME
RESERVED
RESERVED
FREE_CLK
Bit Name
FEFI_EN
TQ_EN
FX_EN
ER
TABLE 29. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16
Strap, RW
Strap, RW
000, RW
Default
0, RW
0, RW
0, RW
0, RW
1, RW
0, RW
0, RW
0, RW
0, RO
Auto-Crossover in Forced Mode:
1 = Auto-Crossover in Forced Mode Enabled
Allows the device to toggle between MDIX and MDI channels when forced to 10M
or 100M mode. This function is mutually exclusive with the Auto-Negotiation
Enable bit, BMCR[12], and with the Auto-MDIX Enable bit, PHYCR[15]. These
bits should not be set when enabling Auto-crossover.
0 = Normal operation
RESERVED: Must be 0.
Receive Clock:
1 = RX_CLK is free-running.
0 = RX_CLK phase adjusted based on alignment.
100 Mb/s True Quiet Mode Enable:
1 = Transmit True Quiet Mode.
0 = Normal Transmit Mode.
Signal Detect Force PMA:
1 = Forces Signal Detection in PMA.
0 = Normal SD operation.
Signal Detect Option:
1 = Default operation. Link will be asserted following detection of valid signal level
and Descrambler Lock. Link will be maintained as long as signal level is valid. A
loss of Descrambler Lock will not cause Link Status to drop.
0 = Modified signal detect algorithm. Link will be asserted following detection of
valid signal level and Descrambler Lock. Link will be maintained as long as signal
level is valid and Descrambler remains locked.
Descrambler Timeout:
Increase the descrambler timeout. When set, this allows the device to receive
larger packets (>9k bytes) without loss of synchronization.
1 = 2 ms.
0 = 722 µs (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e).
FX Fiber Mode Enable:
This bit is set when the FX_EN strap option is selected for the respective port.
Write PHYCR2[9], SOFT_RESET, after enabling or disabling Fiber Mode via
register access to ensure correct configuration.
1 = Enables FX operation.
0 = Disables FX operation.
Force 100 Mb/s Good Link:
OR’ed with MAC_FORCE_LINK_100 signal.
1 = Forces 100 Mb/s Good Link.
0 = Normal 100 Mb/s operation.
RESERVED: Writes ignored, read as 0.
Far End Fault Indication Mode Enable:
This bit is set when the FX_EN strap option is selected for the respective port.
1 = FEFI Mode Enabled.
0 = FEFI Mode Disabled.
NRZI Bypass Enable:
1 = NRZI Bypass Enabled.
0 = NRZI Bypass Disabled.
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Description