dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 27

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

order to initialize the MDIO interface, the station management
entity sends a sequence of 32 contiguous logic ones on MDIO
to provide the DP83630 with a sequence that can be used to
establish synchronization. This preamble may be generated
either by driving MDIO high for 32 consecutive MDC clock
cycles, or by simply allowing the MDIO pull-up resistor to pull
the MDIO pin high during which time 32 MDC clock cycles are
provided. In addition 32 MDC clock cycles should be used to
re-sync the device if an invalid Start, Opcode, or turnaround
bit is detected.
The DP83630 waits until it has received this preamble se-
quence before responding to any other transaction. Once the
DP83630 serial management port has been initialized no fur-
ther preamble sequencing is required until after a power-on/
reset, invalid Start, invalid Opcode, or invalid turnaround (TA)
bit has occurred.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
10.4.3 Serial Management Preamble Suppression
The DP83630 supports a Preamble Suppression mode as in-
dicated by a one in bit 6 of the Basic Mode Status Register
(BMSR, address 01h.) If the station management entity (i.e.
MAC or other management controller) determines that all
PHYs in the system support Preamble Suppression by re-
turning a one in this bit, then the station management entity
need not generate preamble for each management transac-
tion.
The DP83630 requires a single initialization sequence of 32
bits of preamble following hardware/software reset. This re-
quirement is generally met by the mandatory pull-up resistor
Read Operation
Write Operation
MII Management Serial Protocol
FIGURE 5. Typical MDC/MDIO Write Operation
FIGURE 4. Typical MDC/MDIO Read Operation
TABLE 7. Typical MDIO Frame Format
<idle><start><opcode><device addr><reg addr><turnaround><data><idle>
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
27
Turnaround is defined as an idle bit time inserted between the
Register Address field and the Data field. To avoid contention
during a read transaction, no device shall actively drive the
MDIO signal during the first bit of Turnaround. The addressed
DP83630 drives the MDIO with a zero for the second bit of
turnaround and follows this with the required data.
shows the timing relationship between MDC and the MDIO as
driven/received by the Station (STA) and the DP83630 (PHY)
for a typical register read access.
For write transactions, the station management entity writes
data to the addressed DP83630 thus eliminating the require-
ment for MDIO Turnaround. The Turnaround time is filled by
the management entity by inserting <10>.
timing relationship for a typical MII register write access.
on MDIO in conjunction with a continuous MDC, or the man-
agement access made to determine whether Preamble Sup-
pression is supported.
While the DP83630 requires an initial preamble sequence of
32 bits for management initialization, it does not require a full
32-bit sequence between each subsequent transaction. A
minimum of one idle bit between management transactions is
required as specified in the IEEE 802.3u specification.
10.5 PHY CONTROL FRAMES
The DP83630 supports a packet-based control mechanism
for use in situations where the Serial Management Interface
Figure 6
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shows the
Figure 4