dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 37
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dp83630sqx
Manufacturer Part Number
dp83630sqx
Description
Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP83630SQX.pdf
(126 pages)
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13.2 FIBER NETWORK CIRCUIT
Figure 10
pair interface.
13.3 ESD PROTECTION
Typically, ESD precautions are predominantly in effect when
handling the devices or board before being installed in a sys-
tem. In those cases, strict handling procedures need be im-
plemented during the manufacturing process to greatly
reduce the occurrences of catastrophic ESD events. After the
system is assembled, internal components are less sensitive
from ESD events.
The network interface pins are more susceptible to ESD
events.
13.4 CLOCK IN (X1) RECOMMENDATIONS
The DP83630 supports an external CMOS level oscillator
source or a crystal resonator device.
shows the recommended circuit for a 100 Mb/s fiber
FIGURE 10. 100 Mb/s Fiber Pair Interface
37
Oscillator
If an external clock source is used, X1 should be tied to the
clock source and X2 should be left floating.
The CMOS 25 MHz oscillator specifications for MII Mode are
listed in
oscillator specifications are listed in
mode, it is not recommended that the system clock out, Pin
24, be used as the reference clock to the MAC without first
verifying the interface timing. See AN-1405 for more details.
Crystal
A 25 MHz, parallel, 20 pF load crystal resonator should be
used if a crystal source is desired.
connection for a crystal resonator circuit. The load capacitor
values will vary with the crystal vendors; check with the ven-
dor for the recommended loads.
The oscillator circuit is designed to drive a parallel resonance
AT cut crystal with a minimum drive level of 100 µW and a
Table
9. For RMII Slave Mode, the CMOS 50 MHz
Figure 11
Table
10. For RMII Slave
shows a typical
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