peb20954 Infineon Technologies Corporation, peb20954 Datasheet - Page 107

• Manufacturer Part Number: peb20954
• Description: Smart Integrated Digital Echo Canceller Sidec
• Manufacturer: Infineon Technologies Corporation

UCCPOLL
TSMPOLL
SFATSES[2:0] (Addr.: 36H): Super frame alarm and requested timeslot en/disable
status
TSENVALID
TSEN
SFA
SOTP[6:0] (Addr.: 3DH): Send path output test pattern
SOTP[6:0]
TESTSTAT[7:0] (Addr.: 3EH): Background test status signals
This register contains results of background test of timeslot defined in register ATE
DISPS
DIS
NLP
FREEZE
HRESET
Preliminary Data Sheet
DISPS
-
-
SOTP[6] SOTP[5] SOTP[4] SOTP[3] SOTP[2] SOTP[1] SOTP[0]
DIS
-
’1’: UCC status
’1’: Timeslot monitor status
’1’: TSEN value for the requested TS in register ATE is valid
’0’: TSEN value not valid since channel defined in register ATE
’1’: requested TS in register ATE is enabled, no test recommended
’0’: requested TS in register ATE is disabled, test permissible
’1’: alarm, because not synchronized to PCM30 superframe
’0’: no alarm, because either synchronization to PCM superframe or
Result of background test of timeslot defined in register ATE,
amplitude A-/µ-Law encoded
'1': 2100 Hz tone with phase shift detected
'0': no 2100 Hz tone with phase shift detected
'1': 2100 Hz tone detected
'0': no 2100 Hz tone detected
'1': NLP active
'0': NLP disabled (bypassed)
'1': H-Register frozen
'0': H-Register not frozen
'1': H-Register reset
is not detected yet
TS16 CAS evaluation is deactivated
(Bit CONFTS16.ENTS16 = ’0’)
NLP
-
FREEZE HRESET
-
107
-
VALID
TSEN
ERL
Register Description
TSEN
FCM
PEB 20954
PEF 20954
SPEECH
SFA
NO
04.99