peb20954 Infineon Technologies Corporation, peb20954 Datasheet - Page 86

• Manufacturer Part Number: peb20954
• Description: Smart Integrated Digital Echo Canceller Sidec
• Manufacturer: Infineon Technologies Corporation

Preliminary Data Sheet
IMASKFRN[7:0] (Addr.: 66H): Interrupt Mask for channel individual UCC frames (FRN),
Reset value = 00H
IMASKFRN[7:0]
Note: In 128 ms mode the change of an unmasked bit in one of the channel individual
UCC frames generates an interrupt condition only if the frame number of the changed
frame corresponds to one of the 16 processed channels or bit UCCFRS.128FRSEN is
set to ’1’.
TESTTIMER[1:0] (Addr.: 37H): P Test and Timer, write protected,
Reset value = 00H
UPTEST
RUNTIMER
* Note: For using the timer in conjunction with the self-test, the timer should be started
at the same time the test is activated.
ATE[4:0] (Addr.: 35H): Address of Test-channel, write protected, Reset value = 00H
ATE [4:0]
Note: A test can only be executed in a disabled channel. Therefore, it must be
determined whether the channel is en/disabled. Once a test is started it can only be
IMASK
FRN[7]
-
-
IMASK
FRN[6]
-
-
Each activated (set to ’1’) mask bit prevents the generation of an
UCC interrupt at a change of the corresponding bit in any channel
individual UCC frame FRN.
enable for the self test:
’1’: self test is executed in the test channel selected by ATE and
’0’: self test disabled
’1’: start timer*
’0’: disable/stop timer*
On the one hand this value corresponds to the channel for which the
determination is made if it is en/disabled (result in bit TSEN in register
SFATSES). On the other hand, the value corresponds to the channel
in which the test is executed.
values of register CTRLTEST are evaluated. This channel is
bypassed according to Figure 9 with "BYPASS".
IMASK
FRN[5]
-
-
IMASK
FRN[4]
ATE[4]
-
86
IMASK
FRN[3]
ATE[3]
-
FRN[2]
IMASK
ATE[2]
-
Register Description
UPTEST
FRN[1]
IMASK
ATE[1]
PEB 20954
PEF 20954
FRN[0]
IMASK
TIMER
ATE[0]
RUN
04.99