peb20954 Infineon Technologies Corporation, peb20954 Datasheet - Page 75

• Manufacturer Part Number: peb20954
• Description: Smart Integrated Digital Echo Canceller Sidec
• Manufacturer: Infineon Technologies Corporation

SOATTMOD
ROATTEN
ROATTMOD
DYNSUB
INVERRSIGN
CONFLAW[3:0] (Addr.: 3FH): Global configuration of PCM encoding law,
write protected, Reset value = 00H
For explanation of A/ -Law Conversion functions see also Figure 8.
CHIND
GCONVDISLAW Determines the valid PCM law if the PCM-Law conversion of an
GALAWNE
GALAWFE
Preliminary Data Sheet
-
-
Allows global configuration of near end PCM-Law:
’0’: Attenuation of send path output is disabled for all channels
’1’: Attenuation of send path output is 2.5 dB if enabled
’0’: Attenuation of send path output is 6 dB if enabled
’1’: Attenuation of receive path output enabled and controlled by
’0’: Attenuation of receive path output is disabled for all channels
’1’: Attenuation of receive path output is 2.5 dB if enabled
’0’: Attenuation of receive path output is 6 dB if enabled
’1’: The subtractor dynamically attenuates the send output signal if
’0’: The subtractor operates in linear mode
’1’: Sign of error signal (Echo + Near end speech) is
’0’: Sign of error signal (Echo + Near end speech) is
’1’: Enables individual PCM encoding law settings for each channel
’0’: Enables global PCM encoding law configuration for all channels
individual channel is disabled by any source ( P, UCC or serial
control signal) if CHIND = ’0’
’1’: All PCM channels for which conversion is disabled are A-Law
’0’: All PCM channels for which conversion is disabled are -Law
’1’: A-Law PCM encoding at near end side (RO and SI)
’0’: -Law PCM encoding at near end side (RO and SI)
Allows global configuration of far end PCM-Law:
’1’: A-Law PCM encoding at far end side (RI and SO)
canceller en/disable
echo canceller en/disable
difference is derived from large signal levels
inverted (normal operation)
not inverted (incorrect operation, for test only)
by bits 7 to 5 of the individual control registers CHCTRL 0 to 31
by bits 2 to 0 of this register
en/decoded*
en/decoded*
if CHIND = ’0’ and CONVDIS = ’0’
if CHIND = ’0 and CONVDIS = ’0’
-
-
75
CHIND
DISLAW
GCONV
Register Description
GALAW
NE
PEB 20954
PEF 20954
GALAW
FE
04.99