peb20954 Infineon Technologies Corporation, peb20954 Datasheet - Page 42

• Manufacturer Part Number: peb20954
• Description: Smart Integrated Digital Echo Canceller Sidec
• Manufacturer: Infineon Technologies Corporation

Preliminary Data Sheet
Note: Above values are examples only. PCM frame alignment with respect to the first
detection of an active SYNCI (or SYNCO: If no SYNCI is applied, SYNCO takes over the
part and role of SYNCI) with the falling edge of SCLKI can be configured by writing to the
registers RIALIGN, SIALIGN an SOALIGN. For finer adjustments, the valid bit phase of
the PCM signals at the first detection of an active SYNCI with the falling edge of SCLKI
can be configured by writing to the register PHALIGN. The configured frame and bit
phase alignment always denotes the beginning of the ideal bit phase (no signal delay) at
the falling edge of SCLKI.
PCM inputs are always sampled with the falling edge of SCLKI at the beginning of bit
phase 2, outputs are clocked with the falling edge of SCLKI at the beginning of bit phase
0. Unless not bypased the PCM output RO has a fixed delay of one PCM frame (125 s)
with respect to RI.
.
Figure 20
Figure 21 illustrates the synchronization of the 2048 kBit/s PCM and UCC signal for a
low active SYNCI signal with respect to the internal 8192 kHz SCLKI signal. If SYNCI is
sampled with the falling edge of SCLKI (CONFCC.SSCLKEDGE=’0’) this edge is the
synchronization point for PCM and UCC signals. If SYNCI is sampled with the rising
edge of SCLKI (CONFCC.SSCLKEDGE=’1’) the next falling SCLKI edge is the
synchronization point for PCM and UCC signals. The SYNCO signal may only be used
instead of the SYNCI signal if the UCC Interface is not used
RO
SO
RI
SI
Bit 6
Bit 6
Bit 7
Delay of PCM Signals
Bit 7
4
5
Bit 5
Bit 6
Bit 5
6
42
Bit 6
Bit 4
Bit 5
Bit 4
Operational Description
Bit 5
Bit 5
PEB 20954
PEF 20954
7
Bit 3
Bit 4
Bit 4
04.99