peb20954 Infineon Technologies Corporation, peb20954 Datasheet - Page 83

• Manufacturer Part Number: peb20954
• Description: Smart Integrated Digital Echo Canceller Sidec
• Manufacturer: Infineon Technologies Corporation

RLISTEN
ENTUCCO
ENDISHW
SELFX [1:0]
ENSMLPHW
RSWCTRL
Preliminary Data Sheet
This bit is only active in Reflect Mode which can be configured via bit
CONFUCC.RSWCTRL or SMLP bit of UCC Interface.
’1’: UCCI input data will be transferred to IRAM and interrupt will be
’0’: Normal operation: No data is transferred to IRAM, no interrupts
’1’: Control signal for external tristate buffer TUCCO is enabled for
’0’: Tri-State-Buffer control signal TUCCO is disabled, i.e. = ’1’
’1’: The UCC DIS-Bit (Bit 4) of associated channel (see Figure 10) is
’0’: disable special handling of the DIS-Bit (Bit 4) for channel
Selects the UCC bit for the flexible control bit (FX-Bit)
"11" : UCC-Bit 2 is selected
"10" : UCC-Bit 1 is selected
"01" : UCC-Bit 0 is selected
"00" : No UCC-Bit is selected, i.e. UCC FX-Bit is disabled
Enables special handling of the SMLP bit in the special frame FRS
by hardware if the special frame mode is enabled (Bit NOFRS = ’0’)
’1’: The reflection of UCCI to UCCO is activated by the hardware at
’0’: normal operation, reflection control by bit RSWCTRL
Only effective if ENSMLPHW = ’0’, Reflection control by software.
’1’: The reflection of UCCI to UCCO is activated by the software, not
generated
are generated except by SMLP bit in UCC special frame if
unmasked.
processed channels only (all 32 channels in 64 ms mode or 16
channels in 128 ms mode if bit UCCFRS.128FRSEN is set to
’1’). The mode depends on setting of Pins MODE1 and MODE0.
used for disabling of the associated channel.
individual UCC frames by hardware
the beginning of the next channel individual frame after the bit
SMLP in FRS (UCC Special Frame) changes from ’0’ to ’1’. The
value of the current FRS is the last that is transferred to IRAM, all
the following FRS’s will no longer be transferred to the IRAM.
Only a change of the SLMPbit in FRS is indicated by an interrupt
if not maked by IMASKFRS[7]. Additionally the current status of
the channel individual control bits DIS-Bit and FX-Bit is frozen.
This reflection is deactivated with the beginning of the next
channel individual frame after the FRS, in which the hardware
detects a ’1’ to ’0’ change of the SMLP bit. The value of this FRS
is transferred to the IRAM.
by the hardware via SMLP bit evaluation. Only a change of the
SLMP in FRS is indicated, and the current status of the channel
individual control bits DIS-Bit and FX-Bit is frozen.
The timing for de/activation of the reflection depends solely on
83
Register Description
PEB 20954
PEF 20954
04.99