pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 168
pxf4333
Manufacturer Part Number
pxf4333
Description
Abm 3g Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PXF4333.pdf
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Register 10 UA5RXHD1/DA5RXHD1
•
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
•
Header octets three and four of first ATM cell of AAL5 packet.
The ABM-3G SAR unit does not interpret these bit fields, but copies them from ATM
cells that are extracted during AAL5 packet reassembly process. Extracted cells are
forwarded from the ABM-3G like any cell to be transmitted by the respective UTOPIA
Interface. Thus, the bit field usage depends on the selected LCI mapping mode in the
particular application. From scheduler point of view the reassembly unit is addressed as
UTOPIA port number 30
VCI(11:0)
or
LCI(11:0)
Data Sheet
15
7
Upstream/Downstream AAL5 Receive Header 1 Registers
14
The meaning of this bit field depends on the selected LCI mapping
mode in Register 110: MODE1:
MODE1->LCIMOD(1:0):
’00’
’01’
’10’
’11’
6
VCI(3:0),
VCI(3:0),
LCI(3:0),
Read/Write
0000
UA5RXHD1 0C
Read by CPU
VCI(3:0)
H
.
H
13
5
VCI transparent mode: VCI(11:0)
VCI Address translated mode: LCI(11:0)
VCI transparent mode: VCI(11:0)
VCI transparent mode: VCI(11:0)
H
12
4
VCI(11:4),
VCI(11:4),
LCI(11:4),
VCI(11:4)
168
DA5RXHD1 1C
11
3
PT(2:0)
10
2
Register Description
H
PXF 4333 V1.1
9
1
2001-12-17
ABM-3G
CLP
8
0
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