pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 312

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pxf4333

Manufacturer Part Number
pxf4333
Description
Abm 3g Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
Register 110 MODE1
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
SWRES
CPR(1:0)
Data Sheet
SWRES
WGS
15
7
ABM-3G Mode 1 Register
14
Software Reset (clears automatically after four cycles).
This bit is automatically cleared after execution.
’SWRES’ controls reset of all ABM-3G units.
1
(0)
Cell Pointer Ram Size configuration
(see also
00
01
10
11
Note: The Cell Pointer RAM Size should be programmed during
6
0
0
Read/Write
0000
MODE1
Written and Read by CPU
initialization and should not be changed during operation.
H
13
Table 7-3 "External RAM Sizes" on Page
5
0
CPR(1:0)
Starts internal reset procedure
self-clearing
256k pointer entries per direction
(corresponds to 256k cells in each cell storage RAM)
128k pointer entries per direction
(corresponds to 128k cells in each cell storage RAM)
64k pointer entries per direction
(corresponds to 64k cells in each cell storage RAM)
reserved
EE
BIP8
H
12
4
312
MERGE
CRC10
VC
11
3
LCItog
RAM
INIT
10
2
Register Description
SDRAM
INIT
PXF 4333 V1.1
LCIMOD(1:0)
9
1
177)
2001-12-17
ABM-3G
CORE
8
0

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