pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 263
pxf4333
Manufacturer Part Number
pxf4333
Description
Abm 3g Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PXF4333.pdf
(361 pages)
- Current page: 263 of 361
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Register 72 UECRI/DECRI
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
MaxBurstS(3:0)
ECIntRate(9:0)
Refer to
Page 109
Data Sheet
Section 4.2.2.4 “Programming the SDRAM Refresh Empty Cell Cycles” on
15
7
for the calculation of ECIntRate and ECFracRate
Upstream/Downstream Empty Cycle Rate Integer Part Registers
MaxBurstS(3:0)
14
Maximum Burst size for a Scheduler Block
Refer to
Rates” on Page 106
Integer part of Empty Cycle Rate
The empty cycles are required by internal logic to perform the
refresh cycles of the SDRAMS.
Minimum value is 10
configuration.
6
Read/Write
0000
UECRI
Written by CPU for global Scheduler configuration
H
Section 4.2.2.2 “Programming the Scheduler Block
13
5
A2
H
ECIntRate(7:0)
12
4
H
263
and should be programmed during
DECRI
11
Unused(1:0)
3
10
2
BA
Register Description
H
ECIntRate(9:8)
PXF 4333 V1.1
9
1
2001-12-17
ABM-3G
8
0
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