pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 236
pxf4333
Manufacturer Part Number
pxf4333
Description
Abm 3g Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PXF4333.pdf
(361 pages)
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Register 53 MASK2/MASK3
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
MASK2(15:0)
MASK3(15:0)
Data Sheet
15
7
Table Access Mask Registers 2/3
14
Mask Register 2
Mask Register 3
Mask Registers 0..6 control the Write access from the respective
transfer registers to the internal tables on a per-bit selection basis.
The mask registers correspond to the respective transfer registers
(LCI0..LCI2,
MGT0..MGT2):
0
1
6
Read/Write
0000
MASK2
Written by CPU to control internal table Read/Write access
H
13
5
The dedicated bit of the transfer register overwrites the
table entry during Write.
Does not affect Read access.
The dedicated bit of the transfer register does not
overwrite the table entry during Write.
Does not affect Read access.
TCT0..TCT3,
57
12
MASK(15:8)
4
H
MASK(7:0)
236
11
3
MASK3
QCT0..6,
10
2
Register Description
SBOC0..SBOC4,
PXF 4333 V1.1
9
1
58
H
2001-12-17
ABM-3G
8
0
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