pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 284
pxf4333
Manufacturer Part Number
pxf4333
Description
Abm 3g Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PXF4333.pdf
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Register 89 ERCM0
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
ERCM0(15:0)
Data Sheet
15
7
AVT Table Access Mask Register 0
14
ERC Mask Register 0
ERC Mask Registers 0..1 control the Write access from transfer
registers ERCT0 and ERCT1 to the internal AVT table on a per-bit
selection basis. The mask register bit positions correspond to the
respective transfer registers ERCT0 and ERCT1:
0
1
6
Read/Write
0000
ERCM0
Written by CPU to control internal table Read/Write
access
H
13
5
The dedicated bit of the transfer register overwrites the
table entry during Write.
Does not affect Read access.
The dedicated bit of the transfer register does not
overwrite the table entry during Write.
Does not affect Read access.
CC
H
ERCM0(15:8)
12
ERCM0(7:0)
4
284
11
3
10
2
Register Description
PXF 4333 V1.1
9
1
2001-12-17
ABM-3G
8
0
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