dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 130

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

8.0
TABLE 8-1:
DS70291C-page 128
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1 Data
OC1 – Output Compare 1 Secondary Data
IC2 – Input Capture 2
OC2 – Output Compare 2 Data
OC2 – Output Compare 2 Secondary Data
TMR2 – Timer2
TMR3 – Timer3
SPI1 – Transfer Done
UART1RX – UART1 Receiver
UART1TX – UART1 Transmitter
ADC1 – ADC1 convert done
UART2RX – UART2 Receiver
UART2TX – UART2 Transmitter
SPI2 – Transfer Done
ECAN1 – RX Data Ready
PMP - Master Data Transfer
ECAN1 – TX Data Request
DAC1 - Right Data Output
DAC2 - Left Data Output
Note:
Peripheral to DMA Association
DIRECT MEMORY ACCESS
(DMA)
This data sheet summarizes the features
of
dsPIC33FJ64MCX02/X04,
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a
comprehensive
complement the information in this data
sheet, refer to the “dsPIC33F Family
Reference Manual”, Section 38. “Direct
Memory
(DS70215), which is available from the
Microchip website (www.microchip.com).
DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
the
Access
dsPIC33FJ32MC302/304,
reference
(DMA)
source.
families
(Part
DMAxREQ Register
IRQSEL<6:0> Bits
and
III)”
Preliminary
To
of
0000000
0000001
0000010
0000010
0000101
0000110
0000110
0000111
0001000
0001010
0001011
0001100
0001101
0011110
0011111
0100001
0100010
0101101
1000110
1001110
1001111
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 peripherals that
can utilize DMA are listed in Table 8-1.
Values to Read From
0x0300 (ADC1BUF0)
DMAxPAD Register
0x0226 (U1RXREG)
0x0236 (U2RXREG)
intervention.
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x0608 (PMDIN1)
0x0140 (IC1BUF)
0x0144 (IC2BUF)
0x0440 (C1RXD)
Peripheral
—
—
—
—
—
—
—
—
—
—
—
—
The
© 2009 Microchip Technology Inc.
DMA
0x03F8 (DAC1LDAT)
DMAxPAD Register
0x3F6 (DAC1RDAT)
0x0224 (U1TXREG)
0x0234 (U2TXREG)
Values to Write to
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x0608 (PMDIN1)
0x0180 (OC1RS)
0x0186 (OC2RS)
0x0442 (C1TXD)
0x0182 (OC1R)
0x0188 (OC2R)
Peripheral
controller
—
—
—
—
—
—
—
—
—
can