dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 224

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 17-2:
DS70291C-page 222
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-9
bit 8
bit 7
bit 6-4
bit 3-0
QEOUT
R/W-0
U-0
—
Unimplemented: Read as ‘0’
IMV<1:0>: Index Match Value bits – These bits allow the user application to specify the state of the
QEAx and QEBx input pins during an Index pulse when the POSxCNT register is to be reset.
In x4 Quadrature Count Mode:
In x4 Quadrature Count Mode:
CEID: Count Error Interrupt Disable bit
1 = Interrupts due to count errors are disabled
0 = Interrupts due to count errors are enabled
QEOUT: QEAx/QEBx/INDXx Pin Digital Filter Output Enable bit
1 = Digital filter outputs enabled
0 = Digital filter outputs disabled (normal pin operation)
QECK<2:0>: QEAx/QEBx/INDXx Digital Filter Clock Divide Select Bits
111 = 1:256 Clock Divide
110 = 1:128 Clock Divide
101 = 1:64 Clock Divide
100 = 1:32 Clock Divide
011 = 1:16 Clock Divide
010 = 1:4 Clock Divide
001 = 1:2 Clock Divide
000 = 1:1 Clock Divide
Unimplemented: Read as ‘0’
IMV1 = Required State of Phase B input signal for match on index pulse
IMV0 = Required State of Phase A input signal for match on index pulse
IMV1 = Selects Phase input signal for Index state match (0 = Phase A, 1 = Phase B)
IMV0 = Required state of the selected Phase input signal for match on index pulse
U-0
—
DFLTxCON: DIGITAL FILTER CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
QECK<2:0>
R/W-0
U-0
—
U-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
R/W-0
U-0
—
IMV<2:0>
© 2009 Microchip Technology Inc.
x = Bit is unknown
R/W-0
U-0
—
R/W-0
CEID
U-0
—
bit 8
bit 0