dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 275

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

REGISTER 22-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7-5
bit 4
ADON
R/W-0
R/W-0
ADON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC is off
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
ADDMABM: DMA Buffer Build Mode bit
1 = DMA buffers are written in the order of conversion. The module provides an address to the DMA
0 = DMA buffers are written in Scatter/Gather mode. The module provides a scatter/gather address
Unimplemented: Read as ‘0’
AD12B: 10-bit or 12-bit Operation Mode bit
1 = 12-bit, 1-channel ADC operation
0 = 10-bit, 4-channel ADC operation
FORM<1:0>: Data Output Format bits
For 10-bit operation:
11 = Signed fractional (D
10 = Fractional (D
01 = Signed integer (D
00 = Integer (D
For 12-bit operation:
11 = Signed fractional (D
10 = Fractional (D
01 = Signed Integer (D
00 = Integer (D
SSRC<2:0>: Sample Clock Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = Reserved
101 = Motor Control PWM2 interval ends sampling and starts conversion
100 = GP timer (Timer5 for ADC1) compare ends sampling and starts conversion
011 = Motor Control PWM1 interval ends sampling and starts conversion
010 = GP timer (Timer3 for ADC1) compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing sample bit ends sampling and starts conversion
Unimplemented: Read as ‘0’
SSRC<2:0>
R/W-0
channel that is the same as the address used for the non-DMA stand-alone buffer.
to the DMA channel, based on the index of the analog input and the size of the DMA buffer.
U-0
—
AD1CON1: ADC1 CONTROL REGISTER 1
HC = Cleared by hardware
W = Writable bit
‘1’ = Bit is set
OUT
OUT
ADSIDL
R/W-0
R/W-0
OUT
OUT
= 0000 00dd dddd dddd)
= 0000 dddd dddd dddd)
= dddd dddd dd00 0000)
= dddd dddd dddd 0000)
OUT
OUT
OUT
OUT
= ssss sssd dddd dddd, where s = .NOT.d<9>)
= ssss sddd dddd dddd, where s = .NOT.d<11>)
= sddd dddd dd00 0000, where s =.NOT.d<9>)
= sddd dddd dddd 0000, where s = .NOT.d<11>)
ADDMABM
R/W-0
Preliminary
U-0
—
HS = Set by hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SIMSAM
R/W-0
U-0
—
AD12B
ASAM
R/W-0
R/W-0
x = Bit is unknown
HC,HS
R/W-0
R/W-0
SAMP
FORM<1:0>
DS70291C-page 273
HC, HS
DONE
R/W-0
R/C-0
bit 8
bit 0