dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 83

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

6.1
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04, and dsPIC33FJ128MCX02/X04 family of devices
have two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC configuration bits in the FOSC device
configuration register selects the device clock source.
A warm Reset is the result of all other reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
(COSC<2:0>)
(OSCCON<14:12>) register.
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is detailed below and is shown in
Figure 6-2.
1.
TABLE 6-1:
© 2009 Microchip Technology Inc.
FRC, FRCDIV16, FRCDIVN
FRCPLL
XT
HS
EC
XTPLL
HSPLL
ECPLL
SOSC
LPRC
Note 1:
POR Reset: A POR circuit holds the device in
Reset when the power supply is turned on. The
POR circuit is active until V
threshold and the delay T
Oscillator Mode
2:
3:
System Reset
T
times vary with crystal characteristics, load capacitance, etc.
T
10 MHz crystal and T
T
OSCD
OST
LOCK
bits
= Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, T
OSCILLATOR DELAY
= Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up
= PLL lock time (1.5 ms nominal), if PLL is enabled.
in
the
POR
DD
OST
Startup Delay
Oscillator
crosses the V
has elapsed.
Oscillator
= 32 ms for a 32 kHz crystal.
T
T
T
T
T
T
T
T
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
OSCD
—
—
Control
POR
Preliminary
Startup Timer
Oscillator
T
T
T
T
T
OST
OST
OST
OST
OST
—
—
—
—
—
2.
3.
4.
5.
6.
BOR Reset: The on-chip voltage regulator has
a BOR circuit that keeps the device in Reset
until V
delay T
ensures that the voltage regulator output
becomes stable.
PWRT Timer: The programmable power-up
timer continues to hold the processor in Reset
for a specific period of time (T
BOR. The delay T
power
appropriate level for full-speed operation. After
the delay T
becomes inactive, which in turn enables the
selected oscillator to start generating clock
cycles.
Oscillator Delay: The total delay for the clock to
be ready for various clock source selections is
given in Table 6-1. Refer to Section 9.0
“Oscillator
information.
When the oscillator clock is ready, the processor
begins execution from location 0x000000. The
user application programs a GOTO instruction at
the reset address, which redirects program
execution to the appropriate start-up routine.
The Fail-Safe Clock Monitor (FSCM), if enabled,
begins to monitor the system clock when the
system clock is ready and the delay T
elapsed.
DD
BOR
PLL Lock Time
supplies
crosses the V
PWRT
T
T
T
T
has elapsed. The delay T
LOCK
LOCK
LOCK
LOCK
—
—
—
—
—
—
Configuration”
PWRT
has elapsed, the SYSRST
have
ensures that the system
BOR
OST
stabilized
threshold and the
T
T
T
T
T
T
= 102.4 μs for a
DS70291C-page 81
OSCD
OSCD
OSCD
Total Delay
OSCD
OSCD
OSCD
PWRT
T
T
T
T
T
for
OSCD
OSCD
LOCK
LOCK
LOCK
—
+ T
+ T
+ T
) after a
+ T
+ T
+ T
at
OST
OST
LOCK
OST
OST
OST
more
FSCM
BOR
the
+
+