dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 319

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

28.0
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and
several features intended to maximize application
flexibility and reliability, and minimize cost through
elimination of external components. These are:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
TABLE 28-1:
© 2009 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Note 1:
Address
Note:
dsPIC33FJ128MCX02/X04
2:
SPECIAL FEATURES
This Configuration register is not available on dsPIC33FJ32MC302/304 devices.
When read, these bits will appear as ‘1’. When you write to these bits, set these bits to ‘1’.
This data sheet summarizes the features
of
dsPIC33FJ64MCX02/X04,
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a
comprehensive
complement the information in this data
sheet, refer to the related section in the
“dsPIC33F Family Reference Manual”,
which is available from the Microchip
website (www.microchip.com).
Name
(1)
DEVICE CONFIGURATION REGISTER MAP
the
FWDTEN WINDIS
PWMPIN
dsPIC33FJ32MC302/304,
IESO
Bit 7
reference
FCKSM<1:0>
—
Reserved
RBS<1:0>
RSS<1:0>
devices
HPOL
Bit 6
(2)
families
source.
—
—
include
IOL1WAY
and
JTAGEN
Preliminary
To
LPOL
of
Bit 5
—
—
—
—
—
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
28.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 0xF80000.
The individual Configuration bit descriptions for the
FBS, FGS, FOSCSEL, FOSC, FWDT, and FPOR
Configuration registers are shown in Table 28-2.
Note that address 0xF80000 is beyond the user program
memory space. It belongs to the configuration memory
space (0x800000-0xFFFFFF), which can only be
accessed using table reads and table writes.
The upper byte of all device Configuration registers
should always be ‘1111
appear to be NOP instructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’s to these locations
has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
The Device Configuration register map is shown in
Table 28-1.
ALTI2C
Bit 4
—
—
—
—
—
Configuration Bits
—
Bit 3
—
—
—
—
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
Bit 2
—
1111’. This makes them
GSS<1:0>
FNOSC<2:0>
FPWRT<2:0>
DS70291C-page 317
Bit 1
ICS<1:0>
GWRP
BWRP
SWRP
Bit 0