dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 405

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

Motor Control PWM Module
MPLAB ASM30 Assembler, Linker, Librarian ................... 334
MPLAB ICD 2 In-Circuit Debugger ................................... 335
MPLAB ICE 2000 High-Performance Universal
MPLAB Integrated Development Environment Software .. 333
MPLAB PM3 Device Programmer .................................... 335
MPLAB REAL ICE In-Circuit Emulator System................. 335
MPLINK Object Linker/MPLIB Object Librarian ................ 334
N
NVM Module
O
Open-Drain Configuration ................................................. 158
Output Compare ............................................................... 199
P
Packaging ......................................................................... 382
Peripheral Module Disable (PMD) .................................... 152
PICSTART Plus Development Programmer ..................... 336
Pinout I/O Descriptions (table) ............................................ 15
PMD Module
PORTA
PORTB
Power-on Reset (POR) ....................................................... 82
Power-Saving Features .................................................... 151
Program Address Space ..................................................... 35
Program Memory
Q
Quadrature Encoder Interface (QEI) ................................. 217
Quadrature Encoder Interface (QEI) Module
R
Reader Response ............................................................. 403
Register Map
Registers
© 2009 Microchip Technology Inc.
2-Output Register Map................................................ 47
6-Output Register Map................................................ 46
In-Circuit Emulator .................................................... 335
Register Map............................................................... 61
Details ....................................................................... 383
Marking ..................................................................... 382
Register Map............................................................... 61
Register Map......................................................... 59, 60
Register Map............................................................... 60
Clock Frequency and Switching................................ 151
Construction................................................................ 67
Data Access from Program Memory
Data Access from Program Memory
Data Access from, Address Generation...................... 68
Memory Map ............................................................... 35
Table Read Instructions
Visibility Operation ...................................................... 70
Interrupt Vector ........................................................... 36
Organization................................................................ 36
Reset Vector ............................................................... 36
Register Map............................................................... 47
CRC ............................................................................ 59
Dual Comparator......................................................... 59
Parallel Master/Slave Port .......................................... 58
Real-Time Clock and Calendar................................... 59
AD1CHS0 (ADC1 Input Channel 0 Select ................ 278
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) ... 276
Using Program Space Visibility........................... 70
Using Table Instructions ..................................... 69
TBLRDH ............................................................. 69
TBLRDL .............................................................. 69
Preliminary
AD1CON1 (ADC1 Control 1) .................................... 271
AD1CON2 (ADC1 Control 2) .................................... 273
AD1CON3 (ADC1 Control 3) .................................... 274
AD1CON4 (ADC1 Control 4) .................................... 275
AD1CSSL (ADC1 Input Scan Select Low) ............... 280
AD1PCFGL (ADC1 Port Configuration Low) ............ 280
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 253
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 254
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 254
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 255
CiCFG1 (ECAN Baud Rate Configuration 1)............ 251
CiCFG2 (ECAN Baud Rate Configuration 2)............ 252
CiCTRL1 (ECAN Control 1)...................................... 244
CiCTRL2 (ECAN Control 2)...................................... 245
CiEC (ECAN Transmit/Receive Error Count) ........... 251
CiFCTRL (ECAN FIFO Control) ............................... 247
CiFEN1 (ECAN Acceptance Filter Enable)............... 253
CiFIFO (ECAN FIFO Status) .................................... 248
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) .... 257,
CiINTE (ECAN Interrupt Enable) .............................. 250
CiINTF (ECAN Interrupt Flag) .................................. 249
CiRXFnEID (ECAN Acceptance Filter n
CiRXFnSID (ECAN Acceptance Filter n
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 260
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 260
CiRXMnEID (ECAN Acceptance Filter Mask n
CiRXMnSID (ECAN Acceptance Filter Mask n
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 261
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 261
CiTRBnSID (ECAN Buffer n Standard Identifier)..... 263,
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 262
CiVEC (ECAN Interrupt Code) ................................. 246
CLKDIV (Clock Divisor) ............................................ 145
CORCON (Core Control)...................................... 28, 90
DFLTCON (QEI Control) .......................................... 220
DMACS0 (DMA Controller Status 0) ........................ 134
DMACS1 (DMA Controller Status 1) ........................ 136
DMAxCNT (DMA Channel x Transfer Count)........... 133
DMAxCON (DMA Channel x Control)....................... 130
DMAxPAD (DMA Channel x Peripheral Address) .... 133
DMAxREQ (DMA Channel x IRQ Select) ................. 131
DMAxSTA (DMA Channel x RAM Start Address A) . 132
DMAxSTB (DMA Channel x RAM Start Address B) . 132
DSADR (Most Recent DMA RAM Address) ............. 137
I2CxCON (I2Cx Control)........................................... 229
I2CxMSK (I2Cx Slave Mode Address Mask)............ 233
I2CxSTAT (I2Cx Status) ........................................... 231
IFS0 (Interrupt Flag Status 0) ............................. 94, 101
IFS1 (Interrupt Flag Status 1) ............................. 96, 103
IFS2 (Interrupt Flag Status 2) ............................. 98, 105
IFS3 (Interrupt Flag Status 3) ............................. 99, 106
IFS4 (Interrupt Flag Status 4) ........................... 100, 107
INTCON1 (Interrupt Control 1) ................................... 91
INTCON2 (Interrupt Control 2) ................................... 93
INTTREG Interrupt Control and Status Register ...... 125
IPC0 (Interrupt Priority Control 0) ............................. 108
IPC1 (Interrupt Priority Control 1) ............................. 109
IPC11 (Interrupt Priority Control 11) ......................... 118
IPC14 (Interrupt Priority Control 14) ......................... 119
IPC15 (Interrupt Priority Control 15) ......................... 120
IPC16 (Interrupt Priority Control 16) ......................... 121
IPC17 (Interrupt Priority Control 17) ......................... 122
258
Extended Identifier) .......................................... 257
Standard Identifier) ........................................... 256
Extended Identifier) .......................................... 259
Standard Identifier) ........................................... 259
264, 266
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