dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 323

• Manufacturer Part Number: dspic33fj128mc204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

28.2
All
dsPIC33FJ64MCX02/X04, and dsPIC33FJ128MCX02/
X04 devices power their core digital logic at a nominal
2.5V. This can create a conflict for designs that are
required to operate at a higher typical voltage, such as
3.3V. To simplify system design, all devices in the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04,
and dsPIC33FJ128MCX02/X04 family incorporate an
on-chip regulator that allows the device to run its core
logic from V
The regulator provides power to the core from the other
V
(less than 5 Ohms) capacitor (such as tantalum or
ceramic) must be connected to the V
(Figure 28-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Table 31-13 located in Section 31.0
“Electrical Characteristics”.
On a POR
voltage regulator to generate an output voltage. During
this time, designated as T
disabled. T
resumes operation after any power-down.
FIGURE 28-1:
© 2009 Microchip Technology Inc.
DD
Note:
Note 1: These are typical operating voltages. Refer
pins. When the regulator is enabled, a low-ESR
On-Chip Voltage Regulator
of
C
,
2: It is important for the low-ESR capacitor to
EFC
STARTUP
it takes approximately 20 μs for the on-chip
It is important for the low-ESR capacitor to
be placed as close as possible to the
V
DD
CAP
to Section TABLE 31-13: “Internal Volt-
age Regulator Specifications” located in
Section 31.1 “DC Characteristics” for
the full operating ranges of V
V
be placed as close as possible to the
V
.
3.3V
DDCORE
CAP
/V
the
/V
DDCORE
is applied every time the device
DDCORE
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
.
V
V
V
DD
CAP
SS
dsPIC33F
STARTUP
pin.
/V
dsPIC33FJ32MC302/304,
pin.
DDCORE
, code execution is
CAP
(1)
DD
/V
and V
DDCORE
CAP
Preliminary
/
pin
28.3
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage V
pose of the BOR module is to generate a device Reset
when a brown-out condition occurs. Brown-out condi-
tions are generally caused by glitches on the AC mains
(for example, missing portions of the AC cycle wave-
form due to bad power transmission lines, or voltage
sags due to excessive current draw when a large
inductive load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit, if enabled, contin-
ues to operate while in Sleep or Idle modes and resets
the device should VDD fall below the BOR threshold
voltage.
BOR: Brown-Out Reset
CAP
/V
DDCORE
DS70291C-page 321
. The main pur-