r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 193

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

6.3.5
CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals (CSn) and address signals is to be extended. Extending the assertion period of the
CSn and address signals allows flexible interfacing to external I/O devices.
• CSACRH
• CSACRL
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
Bit Name
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
CS and Address Signal Assertion Period Control 1
These bits specify whether or not the T
be inserted (see figure 6.3). When an area for
which the CSXHn bit is set to 1 is accessed, a
one-state T
address signals are asserted, is inserted before
the normal access cycle.
0: In area n basic bus interface access, the CSn
1: In area n basic bus interface access, the CSn
Description
CS and Address Signal Assertion Period Control 2
These bits specify whether or not the T
shown in figure 6.3 is to be inserted. When an
area for which the CSXTn bit is set to 1 is
accessed, a one-state T
CSn and address signals are asserted, is inserted
after the normal access cycle.
0: In area n basic bus interface access, the CSn
1: In area n basic bus interface access, the CSn
and address assertion period (T
extended
and address assertion period (T
and address assertion period (T
extended
and address assertion period (T
h
Rev. 1.00 Sep. 19, 2008 Page 163 of 1342
cycle, in which only the CSn and
Section 6 Bus Controller (BSC)
t
cycle, in which only the
REJ09B0467-0100
h
h
t
t
) is not
) is extended
) is not
) is extended
h
t
(n = 7 to 0)
(n = 7 to 0)
cycle
cycle is to