r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 338

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

Section 6 Bus Controller (BSC)
6.15.4
When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before
the BACK signal.
This will occur if the next external access request or CBR refresh request occurs while internal bus
arbitration is in progress after the chip samples a low level of BREQ.
6.15.5
(1)
Be sure to set the clock to be connected to the synchronous DRAM to SDRAMφ.
(2)
In the continuous synchronous DRAM space, insertion of the wait state by the WAIT pin is
disabled regardless of the setting of the WAITE bit in BCR.
(3)
This LSI cannot carry out the bank control of the synchronous DRAM. All banks are selected.
(4)
The burst read/burst write mode of the synchronous DRAM is not supported. When setting the
mode register of the synchronous DRAM, set to the burst read/single write and set the burst length
to 1.
(5)
When connecting a synchronous DRAM having CAS latency of 1, set the BE bit to 0 in the
DRAMCR.
Note: The synchronous DRAM interface is not supported by the H8S/2456 Group and H8S/2454
Rev. 1.00 Sep. 19, 2008 Page 308 of 1342
REJ09B0467-0100
Connection Clock
WAIT Pin
Bank Control
Burst Access
CAS Latency
Group.
BREQO Output Timing
Notes on Usage of the Synchronous DRAM