r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 377

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

7.5.4
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in
DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to
a single transfer request, and this is executed the number of times specified in ETCRL. On
completion of the specified number of transfers, MAR and ETCRL are automatically restored to
their original settings and operation continues. One address is specified by MAR, and the other by
IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7
summarizes register functions in repeat mode.
Table 7.7
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of
transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when
H'00 is set in both ETCRH and ETCRL, is 256.
Register
23
23
H'FF
Repeat Mode
15
7
7
ETCRAH
ETCRAL
Register Functions in Repeat Mode
MAR
IOAR
0
0
0
0
DTDIR = 0 DTDIR = 1 Initial Setting
Source
address
register
Destination
address
register
Holds number of
transfers
Transfer counter
Function
Destination
address
register
Source
address
register
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Fixed
Number of transfers Decremented every
Rev. 1.00 Sep. 19, 2008 Page 347 of 1342
Section 7 DMA Controller (DMAC)
Operation
Incremented/
decremented every
transfer.
Initial setting is
restored when the
value reaches
H'0000
Fixed
transfer.
Loaded with
ETCRH value when
the value reaches
H'00
REJ09B0467-0100