r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 299

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

(3)
In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed
with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR
= H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR =
H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is
entered, in which the bus controller and I/O port clocks are also stopped.
As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If
synchronous DRAM is connected to the external address space and DRAM data is to be retained
in sleep mode, the ACSE bit must be cleared to 0 in MSTPCR.
(4)
When a transition is made to normal software standby, the PALL command is not output. If
synchronous DRAM is connected and DRAM data is to be retained in software standby, self-
refreshing must be set.
DQMU, DQML
Precharge-sel
Address bus
Figure 6.70 Example of Timing when Precharge Time after Self-Refreshing Is Extended
SDRAM
Data bus
CKE
RAS
CAS
Refreshing and All-Module-Clocks-Stopped Mode
Software Standby
WE
φ
φ
by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)
Software
standby
NOP
T
Rc2
T
Rp1
T
Rp2
Column address
PALL
T
p
Rev. 1.00 Sep. 19, 2008 Page 269 of 1342
Continuous synchronous DRAM space write
Row address
Row address
ACTV
T
r
Section 6 Bus Controller (BSC)
T
NOP
c1
Column address
NOP
T
REJ09B0467-0100
cl
NOP
T
c2