r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 671

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

10.15.4 Port G Open Drain Control Register (PGODR)
PGODR specifies the output type of each port G pin.
10.15.5 Pin Functions
Port G pins also function as the pins for JTAG inputs and bus control signal I/Os. The
correspondence between the register specification and the pin functions is shown below.
• PG6/BREQ-A/TDI*
Notes: 1. Supported only in the 145-pin package.
Bit
7
6
5
4
3
2
1
0
Operating mode
EXPE
BRLE
BREQS
PG6DDR
Pin function
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQS in PFCR4, and bit
PG6DDR.
Bit Name

PG6ODR
PG5ODR
PG4ODR
PG3ODR
PG2ODR
PG1ODR
PG0ODR
2. TDI input when BSCANE pin = 1 in the 145-pin package.
BRLE = 1 and
input
PG6
BRLE = 0 or
BREQS = 1
0
0
0
0
0
0
0
0
0
Initial Value
1
output
PG6
1
1, 2, 4

BREQS = 0
BRLE = 1
BREQ-A
R/W

R/W
R/W
R/W
R/W
R/W
R/W
R/W
input
and

Description
Reserved
This bit is always read as 0. Only the initial value
should be written to this bit.
When not specified for BACK-A, BREQO-A, CS0,
CS1, CS2, CS3, CS4, RAS2, RAS3, RAS, or CAS
output, setting a PGODR bit to 1 makes the
corresponding pin an NMOS open-drain output pin,
while clearing a PGODR bit to 0 makes the
corresponding pin a CMOS output pin.
input
PG6
0
TDI input*

0
output
PG6
Rev. 1.00 Sep. 19, 2008 Page 641 of 1342
1
2
BRLE = 1 and
input
PG6
BRLE = 0 or
BREQS = 1
0
7
output
PG6
1
Section 10 I/O Ports
1
REJ09B0467-0100
BREQ-A input
BREQS = 0
BRLE = 1
and
