r4f2456 Renesas Electronics Corporation., r4f2456 Datasheet - Page 755

• Manufacturer Part Number: r4f2456
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2400 Series
• Manufacturer: Renesas Electronics Corporation.

11.4.4
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4, channel 7, or channel 10) counter clock
at overflow/underflow of TCNT_2 (TCNT_5, TCNT_8, or TCNT_11) as set in bits TPSC2 to
TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 11.30 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
Table 11.30 Cascaded Combinations
(1)
Figure 11.18 shows an example of the setting procedure for cascaded operation.
Combination
Channels 1 and 2
Channels 4 and 5
Channels 7 and 8
Channels 10 and 11
Example of Cascaded Operation Setting Procedure
and the counter operates independently in phase counting mode.
Cascaded Operation
<Cascaded operation>
Cascaded operation
Figure 11.18 Cascaded Operation Setting Procedure
Set cascading
Start count
Upper 16 Bits
TCNT_1
TCNT_4
TCNT_7
TCNT_10
[1]
[2]
[1]
[2]
Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
Rev. 1.00 Sep. 19, 2008 Page 725 of 1342
Section 11 16-Bit Timer Pulse Unit (TPU)
Lower 16 Bits
TCNT_2
TCNT_5
TCNT_8
TCNT_11
REJ09B0467-0100