km4132g271b Samsung Semiconductor, Inc., km4132g271b Datasheet - Page 11

• Manufacturer Part Number: km4132g271b
• Description: 128k X 32bit X 2 Banks Synchronous Graphic Ram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

KM4132G271B
SIMPLIFIED TRUTH TABLE
SGRAM vs SDRAM
If DSF is low, SGRAM functionality is identical to SDRAM functionality .
SGRAM can be used as an unified memory by the appropriate DSF control
--> SGRAM=Graphic Memory + Main Memory
Function
3. Auto refresh functions as same as CBR refresh of DRAM.
4. A
5. It is determined at Row active cycle.
6. During burst read or write with auto precharge, new read/(block) write command cannot be issued.
7. Burst stop command is valid only at full page burst length.
8. DQM sampled at positive going edge of a CLK.
9. Graphic features added to SDRAM s original features.
SGRAM
Function
DSF
If "Low" at read, (block) write, Row active and precharge, bank A is selected.
If "High" at read, (block) write, Row active and precharge, bank B is selected.
If A
For A bank write, at A bank Row active, for B bank write, at B bank Row active.
Terminology : Write per bit =I/O mask
masks the data-in at the very CLK(Write DQM latency is 0)
but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
If DSF is tied to low, graphic functions are disabled and chip operates as a 8M SDRAM with 32 DQs.
The automatical precharge without Row precharge command is meant by "Auto".
Auto/Self refresh can be issued only at both precharge state.
whether Normal/Block write operates in write per bit mode or not.
Another bank read/(block) write command can be issued at
9
: Bank select address.
8
is "High" at Row precharge, A
(Block) Write with write per bit mode=Masked(Block) Write
MRS
L
MRS
9
is ignored and both banks are selected.
SMRS
H
Write per bit
Bank Active
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Disable
with
t
L
RP
Bank Active
after the end of burst.
Bank Active
Write per bit
Enable
with
H
Normal
Write
L
Rev. 2.4 (May 1998)
CMOS SGRAM
Write
Block
Write
H