km4132g271b Samsung Semiconductor, Inc., km4132g271b Datasheet - Page 3

• Manufacturer Part Number: km4132g271b
• Description: 128k X 32bit X 2 Banks Synchronous Graphic Ram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

KM4132G271B
128K x 32Bit x 2 Banks Synchronous Graphic RAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Dual bank / Pulse RAS
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the
• Burst Read Single-bit Write operation
• DQM 0-3 for byte masking
• Auto & self refresh
• 16ms refresh period (1K cycle)
• 100 Pin PQFP, TQFP (14 x 20 mm)
• Reverse Type Package offers the best signal routing
Graphics Features
• SMRS cycle.
• Write Per Bit(Old Mask)
• Block Write(8 Columns)
FUNCTIONAL BLOCK DIAGRAM
system clock
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
-. Load mask register
-. CAS Latency (2, 3)
-. Load color register
DQMi
CKE
RAS
CAS
CLK
DSF
WE
CS
DQMi
CONTROL
COLUMN
BLOCK
WRITE
LOGIC
COUNTER
MASK
SERIAL
COLUMN ADDRESS
CONTROL
WRITE
LOGIC
BUFFER
- 3 -
CLOCK ADDRESS(A
ADDRESS REGISTER
ORDERING INFORMATION
* ~G271BQR# / ~G271BTQR# : Reverse Type Package
GENERAL DESCRIPTION
rate Dynamic RAM organized as 2 x 131,072 words by 32 bits,
fabricated with SAMSUNG's high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length, and programmable latencies allows the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
Write per bit and 8 columns block write improves performance in
graphics systems.
MUX
KM4132G271BQ(R)-7
KM4132G271BQ(R)-8
KM4132G271BQ(R)-10
KM4132G271BTQ(R)-7
KM4132G271BTQ(R)-8
KM4132G271BTQ(R)-10
The KM4132G271B is 8,388,608 bits synchronous high data
128Kx32
ARRAY
CELL
BANK SELECTION
ROW DECORDER
ROW ADDRESS
BUFFER
Part NO.
REGISTER
REGISTER
128Kx32
ARRAY
COLOR
CELL
0
MASK
~A
9
)
Max Freq.
COUNTER
REFRESH
143MHz
125MHz
100MHz
143MHz
125MHz
100MHz
DQMi
Rev. 2.4 (May 1998)
CMOS SGRAM
Interface
LVTTL
LVTTL
(i=0~31)
DQi
100 PQFP
100 TQFP
Package