mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 104
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mt9072av2
Manufacturer Part Number
mt9072av2
Description
Octal T1/e1/j1 Framer
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT9072AV2.pdf
(275 pages)
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16.0
The MT9072 JTAG (Joint Test Action Group) interface conforms to the Boundary-Scan standard IEEE1149.1-1990.
This standard specifies a design-for-testability technique called Boundary-Scan test (BST). Figure 10 shows the
BST architecture which is made up of the following four basic elements. See Figure 30 for JTAG timing.
1. Test Access Port (TAP)
2. TAP Controller
3. Instruction Register (IR)
4. Test Data Registers (TDR)
16.1
The Test Access Port (TAP) provides access to the many test functions of the MT9072. It consists of four input pins
and one output pin. The following pins are from the TAP.
Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK signal does not interfere with any
on-chip clocks and thus remains independent. The TCK permits shifting of test data into or out of the
Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip
logic.
Test Mode Select Input (TMS) - The logic signals received at the TMS input are interpreted by the TAP Controller
to control the test operations. The TMS signal is sampled at the rising edge of the TCK pulses. This pin is internally
pulled up to device V
Framer
Test Access Port (TAP)
Input
JTAG (Joint Test Action Group) Operation
Pins
TRST
TDO
TMS
TCK
TDI
DD
when it is not driven from an external source.
TAP
Figure 10 - Boundary Scan Test Circuit Block Diagram
Controller
TAP
Zarlink Semiconductor Inc.
MT9072
104
Instruction Register
Test Data Registers
Device ID Register
Bypass Register
Boundary Scan
Register
Framer
Logic
Core
Data Sheet
Framer
Output
Pins
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