mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 264

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

AC Electrical Characteristics - Transmit Data Link Pin Timing
1
2
3
4
ST-BUS
Bit Cells
2 Mb/s
ST-BUS
Bit Cells
8 Mb/s
CKi
(ST-BUS C16i)
8 Mb/s
CKi
(ST-BUS C4i)
2 Mb/s
TxDLC - Note 2
(Output)
TxDLC - Note 3
(Output)
TxDL
(Input)
Note 1 - TxDLC output applies for every second frame (FPi) pulse (250 us) only
Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y08)
Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y08)
Clock Delay
Enable Delay
Data Setup
Data Hold
Characteristics
Figure 65 - Transmit Data Link Pin Timing
Sym.
Zarlink Semiconductor Inc.
t
t
t
t
CD
ED
DS
DH
MT9072
Min.
100
50
264
t
ED
Typ.
t
CD
Max.
55
55
Units
ns
ns
ns
ns
t
DS
Inputs Data
MT9072
t
CD
150 pF load on TxDLC
150 pF load on TxDLC
t
Test Conditions
DH
t
ED
Data Sheet
V
T
V
V
V
V
T
T
T
T