mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 215

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15-6
Bit
Bit
1
0
5
4
3
2
1
0
RTLOOP
CRCTST
RXFRST
TXFRST
HLOOP
ADTST
Name
HRST
FTST
Name
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
#
not used.
HDLC Reset. When this bit is high, the HDLC and HDLC registers will be reset (HDLC
Control, HDLC Test Control, Address Recognition Byte). This is similar to RESET being
applied, the only difference being that this bit will not be reset. This bit can only be reset by
writing a zero to this location or applying RESET.
Receive Transmit Loopback. When this bit is high, receive to transmit HDLC loopback
will be activated. Receive data, including end of packet indication, but not including flags or
CRC, will be written to the TX FIFO as well as the RX FIFO. When the transmitter is
enabled, this data will be transmitted as though written by the microprocessor. Both good
and bad packets will be looped back. Receive to transmit loopback may also be
accomplished by reading the RX FIFO using the microprocessor and writing these bytes,
with appropriate tags, into the TX FIFO.
CRC Test. This bit allows direct access to the CRC Comparison Register in the receiver
through the serial interface. After testing is enabled, serial data is clocked in until the data
aligns with the internal comparison (16 RXC clock cycles) and then the clock is stopped.
The expected pattern is F0B8 hex. Each bit of the CRC can be
corrupted to allow more efficient testing.
Fifo Test. This bit allows the writing to the RX FIFO and reading of the TX FIFO through
the microprocessor to allow more efficient testing of the FIFO status/interrupt functionality.
This is done by making a TX FIFO write become a RX FIFO write and a RX FIFO read
become a TX FIFO read. In addition, EOP/FA and RQ8/RQ9 are re-defined to be
accessible (i.e. RX write causes EOP/FA to go to RX fifo input; TX read looks at output of
TX fifo through RQ8/RQ9 bits).
Address Recognition Test. This bit allows direct access to the Address Recognition
Registers in the receiver through the serial interface to allow more efficient testing. After
address testing is enabled, serial data is clocked in until the data aligns with the internal
address comparison (16 RXc clock cycles) and then clock is stopped. Then the VADDR bit
in Y1C can be checked.
HDLC Loopback. When high, transmit to receive HDLC loopback will be activated. The
packetized transmit data will be looped back to the receive input. RXEN and TXEN bits
must also be enabled.
Rx Fifo Reset. When high, the RX FIFO will be reset. This causes the receiver to be
disabled until the next reception of a flag. The status register will identify the FIFO as
being empty. However, the actual bit values in the RX FIFO will not be reset.
Transmit FIFO Reset. When high, the TX FIFO will be reset. The Status Register will
identify the FIFO as being empty. This bit will be reset when data is written to the TX
FIFO. However, the actual bit values of data in the TX FIFO will not be reset.
Table 191 - HDLC Test Control(YF3) (E1)
Table 190 - HDLC Control1(YF2) (E1)
Zarlink Semiconductor Inc.
MT9072
215
Functional Description
Functional Description
Data Sheet