mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 254

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

AC Electrical Characteristics - Transmit Data Link Timing
1
2
3
4
1.5 Mb/s
Bit Cells
TXCL
1.5 Mhz Clock
TxDLC - Note 2
(Output)
TxDLC - Note 3
(Output)
TxDL
(Input)
Note 1 - TxDLC output applies for every second frame (FPi) pulse (250 us) only
Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y06)
Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y06)
Note 4- TXCL is an input 1.5 Mhz clock for the PCM24 interface
Note 5- The TXDLC clock is provided one frame before it is used in ESF Mode in Frames 2 4
RXBF
RxDLC
RxDL
Clock Delay
Enable Delay
Data Delay Read
Data Hold Read
Characteristics
Figure 48 - Receive Data Link Functional Diagram
tCD
tED
Figure 47 - Transmit Data Link Pin Timing
Sym.
t
t
t
t
DDR
DHR
CD
ED
Zarlink Semiconductor Inc.
t
DS
Inputs Data
tCD
MT9072
MT9072
Min.
254
t
DH
Typ.
100
100
100
50
Max.
Units
ns
ns
ns
ns
150 pF load on RxDLC
150 pF load on RxDLC
150 pF load on RxDL
150 pF load on RxDL
Test Conditions
Data Sheet
VT
V
V
V
T
T
T