mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 184

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

15-13
7-5
Bit
13
12
11
10
9
8
4
3
2
1
0
TWOSEC Two Second Timer Status. This bit toggles from low to high once every two seconds, and is
ONESEC One Second Timer Status. This bit toggles from low to high once every one second, and is
CRCRF
CRCS1
CRCS2
Name
CALN
T400
###
T1
T2
T8
(#)
##
Table 154 - CRC-4 Timers & CRC-4 Local Status (R Address Y11) (E1)
not used.
synchronous with the applied125 us frame pulse at pin FPi.
synchronous with the applied125 us frame pulse at pin FPi.
Timer 1. If one, indicates that a receive PCM30 link with non-normal operational CRC-4
frames (CSYNC=1 of register address Y10) has persisted for at least 100 ms. This bit is zero
when Timer 2 (T2 of register address Y11) is one. Refer to I.431 Section 5.9.2.2.3.
Timer 2. If one, indicates that a receive PCM30 link with normal operational CRC-4 frames
(CSYNC=0 of register address Y11) has persisted for at least 10 ms. This bit is cleared (zero)
when non-normal operational frames (CSYNC=1) occur. Refer to I.431 Section 5.9.2.2.3.
400 ms Timer Status. This is the 400 ms CRC-4 multiframe alignment timer. This bit initially
changes state from zero to one synchronously with the T8 (register address Y11) bit after the
T8 bit has consecutively toggled 50 times (400 ms). While this condition persists (T8=0101
etc.), the T400 bit continues to change state every 400 ms. The T400 bit is cleared (zero) with
the T8 bit when CRC-4 multiframe synchronization is acquired (CSYNC =0).
8 ms Timer Status. This is the 8 ms CRC-4 multiframe alignment timer. This bit initially
changes state from zero to one synchronously with the CRCRF (register address Y11) bit
when the received PCM30 link CRC-4 multiframe synchronization (CSYNC of register
address Y10) could not be found within the time out period of 8 ms after detecting basic frame
synchronization (BSYNC=0 of register address Y10). While this condition persists
(CRCRF=1), the T8 bit continues to change state every 8 ms. The T8 bit is cleared (zero) with
the CRCRF bit when CRC-4 multiframe synchronization is acquired (CSYNC =0).
not used.
CRC-4 Alignment 2ms Timer. When CRC-4 multiframe alignment has not been achieved
(CSYNC=1 of register address Y10), this bit asynchronously changes state every 2 ms. When
CRC-4 multiframe alignment has been achieved (CSYNC =0), this bit still changes state every
2 ms, but is synchronous with the receive CRC-4 multiframe signal.
CRC-4 Reframe. If one, indicates the received PCM30 link CRC-4 multiframe
synchronization (CSYNC of register address Y10) could not be found within the time out
period of 8 ms after detecting basic frame synchronization (BSYNC of register address Y10).
This bit is cleared (zero) when CRC-4 multiframe synchronization is acquired (CSYNC =0).
Receive CRC-4 Error Status One. If one, the CRC-4 evaluation of the last received PCM30
link submultiframe 1 resulted in an error (the calculated C1,C2,C3,C4 CRC-4 remainder bits
did not match the received CRC-4 remainder C1,C2,C3,C4 bits). If zero, the last
submultiframe 1 was error free. Updated on a submultiframe 1 basis.
Receive CRC-4 Error Status Two. If one, the CRC-4 evaluation of the last received PCM30
link submultiframe 2 resulted in an error (the calculated C1,C2,C3,C4 CRC-4 remainder bits
did not match the received CRC-4 remainder C1,C2,C3,C4 bits). If zero, the last
submultiframe 2 was error free. Updated on a submultiframe 2 basis.
not used.
Zarlink Semiconductor Inc.
MT9072
Functional Description
184
Data Sheet