mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 202

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

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Table 179 - Counter Indication and Counter Overflow Interrupt Status Register (Address Y35) (E1)
Name
CEOI
VEOI
EEOI
PCOI
PEOI
BEII
CEII
VEII
EEII
PEII
#
Frame Alignment Signal (FAS) Bit Error Counter Indication Interrupt. This bit is one
when the corresponding latched status bit (BEIL, register address Y25) is set, and the
corresponding mask bit is unmasked (BEIM, register address Y45). This bit is cleared when
either this register, or the latched status register is read.
CRC-4 Error Counter Overflow Interrupt. This bit is one when the corresponding latched
status bit (CEOL, register address Y25) is set, and the corresponding mask bit is unmasked
(CEOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
CRC-4 Error Counter Indication Interrupt. This bit is one when the corresponding latched
status bit (CEIL, register address Y25) is set, and the corresponding mask bit is unmasked
(CEIM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
Bipolar Violation (BPV) Error Counter Overflow Interrupt. This bit is one when the
corresponding latched status bit (VEOL, register address Y25) is set, and the corresponding
mask bit is unmasked (VEOM, register address Y45). This bit is cleared when either this
register, or the latched status register is read.
Bipolar Violation (BPV) Error Counter Indication Interrupt. This bit is one when the
corresponding latched status bit (VEIL, register address Y25) is set, and the corresponding
mask bit is unmasked (VEIM, register address Y45). This bit is cleared when either this
register, or the latched status register is read.
E-Bit Error Counter Overflow Interrupt. This bit is one when the corresponding latched
status bit (EEOL, register address Y25) is set, and the corresponding mask bit is unmasked
(EEOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
E-Bit Error Counter Indication Interrupt. This bit is one when the corresponding latched
status bit (EEIL, register address Y25) is set, and the corresponding mask bit is unmasked
(EEIM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
PRBS CRC-4 Counter Overflow Interrupt. This bit is one when the corresponding latched
status bit (PCOL, register address Y25) is set, and the corresponding mask bit is unmasked
(PCOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
not used.
PRBS Error Counter Overflow Interrupt. This bit is one when the corresponding latched
status bit (PEOL, register address Y25) is set, and the corresponding mask bit is unmasked
(PEOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
PRBS Error Counter Indication Interrupt. This bit is one when the corresponding latched
status bit (PEIL, register address Y25) is set, and the corresponding mask bit is unmasked
(PEIM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
Zarlink Semiconductor Inc.
MT9072
Functional Description
202
Data Sheet