mt9072av2 Zarlink Semiconductor, mt9072av2 Datasheet - Page 56

• Manufacturer Part Number: mt9072av2
• Description: Octal T1/e1/j1 Framer
• Manufacturer: Zarlink Semiconductor

In T1 mode, the transmit and receive elastic buffers also serve the purpose of rate conversion between the
1.544 Mbit/s line rate and the 2.048 Mbit/s backplane rate. Consequently, in T1 mode the elastic buffers cannot be
bypassed, except for the special case of T1 IMA mode.
Register
Address
Register
Address
Y00
Y13
Y14
Y26
Y36
Y46
YF7
Y00
Y03
Y10
Y14
Y34
Y44
Framing Mode Select
Receive Slip Buffer Status Word
Transmit Slip Buffer Status Word This register provides status bit for transmit slip and its direction
Elastic Store and Excessive Zero
Status Latch
Elastic Store and Excessive Zero
Interrupt Status
Elastic Store and Excessive Zero
Interrupt Mask
Transmit Set Delay Bits
Framing Mode Select
DL,CCS,CAS and Other
Control Register
Sync and CRC-4 Remote
status
Phase Status Indicator
Sync,CRC-4 Remote, Alarm,
MAS and Phase Status Word
Sync,CRC-4 Remote, Alarm,
MAS and Phase Status Word
Interrupt Mask
Register
Table 14 - Registers Related to the Elastic Buffer (T1)
Register
Table 15 - Registers Related to Elastic Store (E1)
Zarlink Semiconductor Inc.
If IMA mode is selected the transmit and receive elastic buffers
are bypassed.
This register provides status bits for receive slip and its direction
word that indicates the phase difference between the ST-BUS
and the PCM24
word that indicates the phase difference between the ST-BUS
and the PCM24.
This register indicates the latched version of the slip indicator
bits from registers Y13 and Y14.
Interrupt status word for the slip indicators.
Interrupt mask bits for the slip indicators.
This register sets a one time delay through the transmit slip
buffer.
If IMA mode is selected the receive elastic buffers are bypassed.
ELAS bit is used to bypass the elastic store, that data at DSTo is
the received. PCM30 data after the HDB3 coding.
RSLP and RSLPD show the slip and the direction of the slip.
This word reflects the delay through the receive elastic store
from the line to the ST-BUS side.
RSLIPI in this register reflects the interrupt due to a slip.
Interrupt mask bits for the slip indicator.
MT9072
56
Description
Description
Data Sheet