zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 108

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

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14.2
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IEEE Standard 1149.1-2001; Test Access Port and Boundary Scan Architecture
IEEE Standard 802.3-2000; Local and Metropolitan Networks CSMA/CD Access Method and Physical Layer
ECTF H.110 Revision 1.0; Hardware Compatibility Specification
H-MVIP (GO-MVIP) Standard Release 1.1a; Multi-Vendor Integration Protocol
MPC8260AEC/D Revision 0.7; Motorola MPC8260 Family Hardware Specification
RFC 768; UDP
RFC 791; IPv4
RFC 2460; IPv6
RFC 1889; RTP
RFC 2661; L2TP
CCITT G.712; TDM Timing Specification (Method 2)
G.823; Control of Jitter/Wander with digital networks based on the 2.048 Mbps hierarchy
G.824; Control of Jitter/Wander with digital networks based on the 1.544 Mbps hierarchy
G.8261; Timing and Synchronization aspects in Packet Networks
ANSI T1.101 Stratum 3/4
Telcordia GR-1244-CORE Stratum 3/4/4e
IETF PWE3 draft-ietf-l2tpext-l2tp-base
IETF PWE3 draft-ietf-pwe3-cesop
RFC4553; Structure-Agnostic TDM over Packet (SAToP)
ITU-T Y.1413 TDM-MPLS Network Interworking
Optional Packet Memory Device - Micron MT55L128L32P1 8 Mb ZBT-SRAM
MSAN-126 Revision B, Issue 4; ST-BUS Generic Device Specification
RFC 1213; MIB II
RFC 1757; Remote Network Monitoring MIB (for SMIv1)
RFC 2819; Remote Network Monitoring MIB (for SMIv2)
RFC 2863; Interfaces Group MIB
External Standards/Specifications
Zarlink Standards
Reference Documents
ZL50110/11/12/14
Zarlink Semiconductor Inc.
108
Data Sheet