zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 46

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

CPU_TA
CPU_DREQ0
CPU_DREQ1
CPU_IREQO
CPU_IREQ1
Signal
Table 15 - CPU Interface Package Ball Definition (continued)
I/O
OT
OT
OT
O
O
AB14
AC15
AE16
AF17
AD16
ZL50110/11/12/14
Package Balls
Zarlink Semiconductor Inc.
46
CPU DMA 0 Request Output Active low
CPU Transfer Acknowledge. Driven from
tri-state condition on the negative clock
edge of CPU_CLK following the
assertion of CPU_CS. Active low,
asserted from the rising edge of
CPU_CLK. For a read, asserted when
valid data is available at CPU_DATA.
The data is then read by the host on the
following rising edge of CPU_CLK. For a
write, is asserted when the
ZL50110/11/12/14 is ready to accept
data from the host. The data is written
on the rising edge of CPU_CLK
following the assertion. Returns to
tri-state from the negative clock edge of
CPU_CLK following the de-assertion of
CPU_CS.
synchronous to CPU_CLK rising edge.
Asserted by ZL50110/11/12/14 to
request the host initiates a DMA write.
Only used for DMA transfers, not for
normal register access.
CPU DMA 1 Request
Active low synchronous to CPU_CLK
rising edge. Asserted by
ZL50110/11/12/14 to indicate packet
data is ready for transmission to the
CPU, and request the host initiates a
DMA read. Only used for DMA transfers,
not for normal register access.
CPU Interrupt 0 Request (Active Low)
CPU Interrupt 1 Request (Active Low)
Description
Data Sheet