zl50110gag2 Zarlink Semiconductor, zl50110gag2 Datasheet - Page 59

• Manufacturer Part Number: zl50110gag2
• Description: 1024 Channel 32 T1/e1, 2 T3/e3 Cesop Processor With Triple Ethernet Interface
• Manufacturer: Zarlink Semiconductor

5.3.2
The ZL50110/11/12/14 is programmable such that the frame/clock polarity and clock alignment can be set to any
desired combination. Table 26 shows a brief summary of four different TDM formats; ST-BUS, H.110, H-MVIP, and
Generic (synchronous mode only), for more information see the relevant specifications shown. There are many
additional formats for TDM transmission not depicted in Table 26, but the flexibility of the port will cover almost any
scenario. The overall data format is set for the entire TDM Interface device, rather than on a per stream basis. It is
possible to control the polarity of the master clock and frame pulse outputs, independent of the chosen data format
(used when operating in synchronous master mode).
H-MVIP
Generic
Format
ST-bus
H.110
Data
Structured TDM Port Data Formats
Table 26 - Some of the TDM Port Formats Accepted by the ZL50110/11/12/14 Family
(Mbps)
2.048
2.048
8.192
8.192
2.048
2.048
8.192
2.048
8.192
Data
Rate
channels
Number
frame
128
128
128
128
per
32
32
32
32
32
of
16.384
16.384
Clock
(MHz)
2.048
4.096
8.192
2.048
4.096
8.192
Freq.
2.048
ZL50110/11/12/14
Zarlink Semiconductor Inc.
Nominal
Frame
Width
Pulse
(ns)
244
244
122
244
244
244
488
122
61
59
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Polarity
Positive
Positive
Frame
Pulse
Falling
Falling
Falling
Falling
Rising
Rising
Rising
Rising
Rising
clock
Frame Boundary
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
edge
Alignment
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
edge of
edge of
frame
Rising
Rising
pulse
clock
clock
Data Sheet
MSAN-126
Standard
(Issue 4)
Release
H-MVIP
Zarlink
Rev B
ECTF
H.110
1.1a